Cirrus Logic CS42L73 - Manual (Page 37)

DS882F1 37
CS42L73
SWITCHING SPECIFICATIONS—DIGITAL MIC INTERFACE
Test conditions: Inputs: Logic 0 = GND = DGND = 0 V, Logic 1 = VL; T
A
= +25 C; C
LOAD
= 30 pF.
Notes:
54. The output clock frequency will follow the master clock (MCLK) rate divided down as per the tables in sections “Digital
Microphone (DMIC) Interface” on page 60 . Any deviation of the Master Clock source from the nominal supported rates
will be directly imparted to the output clock rate by the same factor (e.g., +100 ppm offset in the frequency of MCLK1/
MCLK2 will become a +100 ppm offset in DMIC_CLK).
55. Data is valid at the high-level input voltage (V
IH
) and the low-level input voltage (V
IL
), which are specified in “Digital In-
terface Specifications and Characteristics” on page 35 .
Parameters (Note 2) Symbol Min Max Units
Output Clock (DMIC_CLK) Frequency 1/t
P
- (Note 54) kHz
DMIC_CLK Duty Cycle - 45 55 %
DMIC_CLK Rise Time (10% to 90% of VL) t
r
- 22 ns
DMIC_CLK Fall Time (90% to 10% of VL) t
f
- 10 ns
DMIC_SD Setup Time Before DMIC_CLK Rising Edge (Note 55) t
s(SD-CLKR)
10 - ns
DMIC_SD Hold Time After DMIC_CLK Rising Edge (Note 55) t
h(CLKR-SD)
0 - ns
DMIC_SD Setup Time Before DMIC_CLK Falling Edge (Note 55) t
s(SD-CLKF)
10 - ns
DMIC_SD Hold Time After DMIC_CLK Falling Edge (Note 55) t
h(CLKF-SD)
600 - ps
DMIC_SCLK
DMIC_SD
t
h(CLKR-SD)
t
P
t
r
t
f
t
h(CLKF-SD)
t
s(SD-CLKR)
t
s(SD-CLKF)
V
IH
V
IL
V
90%
V
10%
Figure 11. Digital Mic Interface Timing