Register description, 1 fast mode enable (address 00h), 1 test bits – Cirrus Logic CS42L73 User Manual
Page 81: 1 device i.d. (read only), 3 revision id (address 05h) (read only), 1 alpha revision (read only), 2 metal revision (read only), P 81
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CS42L73
6. REGISTER DESCRIPTION
Registers are read/write except for chip ID, revision, and status registers, which are read only. The following bit defi-
nition tables show bit assignments. The default state of each bit after a power-up sequence or reset is indicated for
each bit description via row shading. Reserved registers must maintain their default state.
6.1
Fast Mode Enable (Address 00h)
6.1.1
Test Bits
6.2
Device ID A and B (Address 01h), C and D (Address 02h), and E (Address 03h) (Read Only)
6.2.1
Device I.D. (Read Only)
Device I.D. code for the CS42L73.
6.3
Revision ID (Address 05h) (Read Only)
6.3.1
Alpha Revision (Read Only)
CS42L73 alpha revision level.
6.3.2
Metal Revision (Read Only)
CS42L73 numeric revision level.
I²C Address: 1001010[R/W]
7
6
5
4
3
2
1
0
FM_EN7
FM_EN6
FM_EN5
FM_EN4
FM_EN3
FM_EN2
FM_EN1
FM_EN0
7
6
5
4
3
2
1
0
DEVIDA3
DEVIDA2
DEVIDA1
DEVIDA0
DEVIDB3
DEVIDB2
DEVIDB1
DEVIDB0
7
6
5
4
3
2
1
0
DEVIDC3
DEVIDC2
DEVIDC1
DEVIDC0
DEVIDD3
DEVIDD2
DEVIDD1
DEVIDD0
7
6
5
4
3
2
1
0
DEVIDE3
DEVIDE2
DEVIDE1
DEVIDE0
Reserved
Reserved
Reserved
Reserved
DEVIDA[3:0]
DEVIDB[3:0]
DEVIDC[3:0]
DEVIDD[3:0]
DEVIDE[3:0]
Part Number
4h
2h
Ah (= L in CS42L73)
7h
3h
CS42L73
7
6
5
4
3
2
1
0
AREVID3
AREVID2
AREVID1
AREVID0
MTLREVID3
MTLREVID2
MTLREVID1
MTLREVID0
AREVID[3:0]
Alpha Revision Level
Ah
A
...
...
Fh
F
MTLREVID[3:0]
Metal Revision Level
0h
0
...
...
Fh
F
Note: The Alpha and Metal revision ID form the complete device revision ID. Example: A0, A1, B0, etc.