3 high-impedance mode, 4 master and slave timing, Cs42l73 – Cirrus Logic CS42L73 User Manual
Page 52
52
DS882F1
CS42L73
• Toggles at external sample rate (Fs
ext
)
• xSP_SDIN
Serial data input
• xSP_SDOUT
Serial data output
4.8.3
High-impedance Mode
The serial ports may be placed on a clock/data bus that allows multiple masters, without the need for ex-
ternal buffers. The 3ST_XSP, 3ST_ASP, and 3ST_VSP bits place the internal buffers for the respective
serial port interface signals in a high-impedance state, allowing another device to transmit clocks and data
without bus contention. When the CS42L73 serial port is a timing slave, its xSP_SCLK and xSP_LRCK I/
Os are always inputs and are thus unaffected by the 3ST_xSP control.
show the busing of the serial port interface for both the master and slave timing
CS42L73 serial port use cases.
4.8.4
Master and Slave Timing
The serial ports can independently operate as either the master of timing or a slave to another device’s
timing. When mastering, xSP_SCLK and xSP_LRCK are outputs, when slaved, they are inputs. Master/
Slave mode is configured by the X_M/S, A_M/S, and V_M/S bits. Note, master mode is not supported
when the PCM interface format is selected (refer to section
In master mode, the xSP_SCLK and xSP_LRCK clock outputs are derived from either the internal MCLK
(MCLK) or (for a subset of SCLK = MCLK modes, refer to section
“SCLK = MCLK Modes” on page 53
)
directly from its source, MCLK1 or MCLK2.
When in slave mode, the supported interface sample rates (Fs
ext
) are as is shown for MCLK = 6.000 MHz
in the table
“Serial Port Rates and Master Mode Settings” on page 53
.
CS42L73 x Interface
Transmitting Device #1
Transmitting Device #2
Receiving Device
xSP_SDOUT
xSP_SCLK,
xSP_LRCK
Note:
x = X, A, or V
3ST_xSP
Figure 25. Serial Port Busing when Mastering Timing
CS42L73 x Interface
Transmitting Device #1
Transmitting Device #2
Receiving Device
3ST_xSP
xSP_SDOUT
xSP_SCLK,
xSP_LRCK
Note:
x = X, A, or V
Figure 26. Serial Port Busing When Slave Timed