Cirrus Logic CS42L73 - Manual (Page 54)

54 DS882F1
CS42L73
4.8.6 Formats
Table 7 lists formats supported on the CS42L73 serial ports:
The XSPDIF and VSPDIF register bits are used to select the format for the XSP and VSP. There is no
selector for the ASP, since it always uses I²S format.
6.5000
8.0000 7.9951 -0.06 11 1100
11.0250 11.0169 -0.07 11 0101
12.0000 11.9926 -0.06 11 0100
16.0000 15.9902 -0.06 10 1100
22.0500 22.0339 -0.07 10 0101
24.0000 23.9852 -0.06 10 0100
32.0000 31.9803 -0.06 01 1100
44.1000 44.0678 -0.07 01 0101
48.0000 47.9705 -0.06 01 0100
6.4000
8.0000 8.0000 0.00 11 1110
11.0250 11.0345 0.09 11 0111
12.0000 12.0000 0.00 11 0110
16.0000 16.0000 0.00 10 1110
22.0500 22.0690 0.09 10 0111
24.0000 24.0000 0.00 10 0110
32.0000 32.0000 0.00 01 1110
44.1000 44.1379 0.09 01 0111
48.0000 48.0000 0.00 01 0110
Notes:
1. Refer to section “Internal Master Clock Generation” on page 42 .
2. See “XSP Master Mode Clock Control Dividers” on page 89 , “ASP Master Mode Clock Control Dividers” on
page 90 , and “VSP Master Mode Clock Control Dividers” on page 92 for details regarding MMCC control.
3. For this row, the xSP_LRCK rate and resulting deviation varies based on the programming of MCLKDIV and
x_SCLK=MCLK. The values given, ValueA/ValueB, are applicable according to the rule set in
Table 6 .
Table 6. Actual xSP_LRCK Rate/Deviation Selector for Note 3
MCLKDIV[2:0] MCLK Divide Ratio x_SCLK=MCLK SCLK=MCLK Mode Applicable Value
xxx x 00b SCLK  MCLK ValueA
xxx x 10b SCLK = MCLK ValueB
000 1 11b SCLK = Pre-MCLK ValueB
010 2 11b SCLK = Pre-MCLK ValueA
Table 7. Supported Serial Port Formats
Serial Port I²S Format PCM Format
XSP  
ASP  x
VSP  
Table 5. Serial Port Rates and Master Mode Settings
MCLK Rate
(MHz) (Note 1)
Standard Audio
Sample Rate (kHz)
Actual Master Mode xSP_
LRCK Rate (Fs
ext
) (kHz)
Deviation (%) Settings for x_
MMCC[5:0] (Note 2)