Cirrus Logic CS42L73 - Manual (Page 56)

56 DS882F1
CS42L73
Mode 1:
– WA may be one or up to all-but-one xSP_SCLK periods wide
– 1st data bit is aligned to WA
Mode 2:
– WA may be one xSP_SCLK period wide
– 1st data bit follows WA
– Last data bit may be aligned to WA
Figure 28. PCM Format—Mode 0
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
16 bits
xSP_SDOUT
xSP_SCLK may stop or continue,
t
extra
= 0 to N xSP_SCLK periods
MSB MSB-1 MSB-2 MSB-3 LSB+2 LSB+1 LSB MSB
1/Fs
ext
 17 xSP_SCLK periods when WA is 1 xSP_SCLK period wide,
 18 xSP_SCLK periods when WA is 2 xSP_SCLK periods wide
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB
t
extra
= 0,
WA is 1 xSP_SCLK period wide,
1/Fs
ext
= 17 xSP_SCLK periods
LSB
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB
t
extra
= 0,
WA is 2 xSP_SCLK periods wide,
1/Fs
ext
= 18 xSP_SCLK periods
LSB
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB
t
extra
= 1 xSP_SCLK period,
WA is 1 xSP_SCLK period wide,
1/Fs
ext
= 18 xSP_SCLK periods
LSB
PCM_SCLK may
stop or continue
MSB-1 MSB-2 MSB-3 LSB+2 LSB+1 LSB
LSB MSB
MSB MSB MSB MSB
Note:
x = X, A, or V
Figure 29. PCM Format—Mode 1
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
16 bits
xSP_SDOUT
xSP_SCLK may stop or continue
MSB MSB-1 MSB-2 MSB-3 LSB+2 LSB+1 LSB MSB
1/Fs
ext
 16 xSP_SCLK periods
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB-1
t
extra
= 0,
1/Fs
ext
= 16 xSP_SCLK periods
LSB
MSB-1
WA may be one or up to all-but-one xSP_SCLK periods wide
MSB LSB+1
t
extra
= 0 to N xSP_SCLK periods
(time between LSB and MSB data)
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB-1
t
extra
= 1 xSP_SCLK period,
1/Fs
ext
= 17 xSP_SCLK periods
LSB MSB LSB+1
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB-1
t
extra
= 2 xSP_SCLK periods,
1/Fs
ext
= 18 xSP_SCLK periods
LSB MSB LSB+1
xSP_SCLK may
stop or continue
Note:
x = X, A, or V