Cirrus Logic CS42L73 - Manual (Page 60)

60 DS882F1
CS42L73
4.10.2 Digital Microphone (DMIC) Interface
The DMIC Interface can be used to collect Pulse Density Modulation (PDM) audio data from the integrated
ADCs of one or two digital microphones. The following sections outline how the interface may be used.
4.10.2.1 DMIC Interface Description
The DMIC Interface consists of a serial-data shift clock output (DMIC_SCLK) and a serial data input
(DMIC_SD). The
“Typical Connection Diagram” on page 17 shows how to connect two digital micro-
phones (Left and Right) to the CS42L73. Note how the clock is fanned out to both digital microphones and
both digital microphone’s data outputs share a single signal line to the CS42L73. To share a line, the dig-
ital microphones tristate their output during one phase of the clock (high or low part of cycle, depending
on how they are configured via their L/R input). Alternating between one digital microphone outputting a
bit of data and then the other microphone outputting a bit of data, the digital microphones time domain
multiplex on the signal data line. Data line contention is avoided by entering the high-impedance tristate
faster than removing it.
If only one digital microphone is to be used, the connections to the remaining digital microphone are un-
changed from those used for two digital microphones.
The DMIC_SD signal is weakly pulled (up to power or down to ground as per table “Digital Pin/Ball I/O
Configurations” on page 16 ) by its CS42L73 input. When the DMIC Interface is active, this pulling is not
strong enough to affect the multiplexed data line significantly while it is in tristate between data slots.
When the interface is disabled and the data line is not driven, the weak pulling will ensure the CS42L73
input avoids the power-consuming mid-rail voltage.
4.10.2.2 DMIC Interface Signaling
The signaling on the DMIC Interface is illustrated in following figure. Notice how the left channel (i.e., A or
DATA1 Channel) data from the “left” microphone is sampled on the rising edge of the clock and the right
channel (i.e., B or DATA2 channel) data from the “right” microphone is sampled on the falling edge.
4.10.2.3 DMIC Interface Powering
The DMIC Interface is powered up or down (via the register controls PDN_ADCx and PDN_DMICx) ac-
cording to the logic shown in
Table 9 .
Note: When the DMIC Interface is off, the DMIC_SCLK pin is set to inactive low.
Table 9. Digital Mic Interface Power States
Control Register States
Digital Mic Interface Power
State PDN_ADCA PDN_DMICA PDN_ADCB PDN_DMICB
1 0 X X On
X X 1 0
Otherwise Off
DMIC_CLK
DMIC_SD
Left
(A, DATA1)
Channel Data
Right
(B, DATA2)
Channel Data
Left
(A, DATA1)
Channel Data
Figure 31. Digital Mic Interface Signaling