Cirrus Logic CS42L73 - Manual (Page 74)

74 DS882F1
CS42L73
To use fast start mode, a set of registers must be written in a certain sequence. To enable fast start mode,
perform the following sequence of register writes:
1. Register 00h = 99h
2. Register 7Eh = 81h
3. Register 7Fh = 01h
4. Register 00h = 00h
To disable fast start mode, perform the following sequence of register writes:
1. Register 00h = 99h
2. Register 7Eh = 81h
3. Register 7Fh = 00h
4. Register 00h = 00h
To use fast start mode to reduce the power up time, write the enable sequence prior to step 4 in the default
power up sequence ( “Power-Up Sequence (xSP to HP/LO)” on page 66 ). After the power up sequence is
completed, write the disable sequence.
To use fast start mode for microphone button short detection with a slow MCLK frequency, write the enable
sequence while PDN=1, then clear the PDN and PDN_MIC2_BIAS bits. Make sure all ADCs and DACs are
powered down.
The following paragraphs describe behavior when using fast start mode.
The speakerphone output, speakerphone line output, and ear speakerphone output paths create an audible
pop during power up if fast start mode is enabled. To avoid hearing this pop on the speaker line output path,
mute the external speaker amplifier connected to the CS42L73 during the period when the pop occurs, and
then unmute the external amplifier afterwards.
Figure 40 shows the pop behavior for fast start mode and the
recommended mute control for the external amplifier.
Also, in fast start mode, bias voltages have slower ramp-up times than normal, which may affect the audio
quality (reduced volume and increased clipping) while the device powers up. This behavior is seen only on
the speakerphone output, speakerphone line output, and ear speakerphone output paths.
Figure 41 and
Table 14 show the approximate time periods when the output audio may be affected.
SPKOUT
SPKLINEOUT
EARSPKOUT
t = 50ms
MUTE
PDN
Figure 40. Fast Start Pop