Cirrus Logic CS42L73 - Manual (Page 14)

14 DS882F1
CS42L73
1.3 Pin/Ball Descriptions
Name Location Description
WLCSP FBGA
MCLK1
MCLK2 A6
D6 B3
B2 High Speed Clock (Input) . Potential clock sources for the converters and the device core. Clock
source for optional serial port mastering.
RESET E6 C9 Reset (Input) . The device enters a low-power mode when this pin is driven low.
SCL C3 A9 Serial Control Port Clock (Input) . Serial clock for the I²C control interfaces.
SDA A3 B9 Serial Control Data (Input/Output) . SDA is the bidirectional data pin for the I²C control interface.
INT D3 B8 Interrupt Request (Output) . Open-drain active low interrupt request output.
LINEINA
LINEINB A1
B2 D8
D9 Analog Line Inputs, A and B (LEFT and RIGHT) (Input) . The full-scale level is specified in the
Analog Input Characteristics specification table.
LINEIN_REF A2 C8
Analog Line Input Pseudodifferential Reference (Input) . Ground reference for the analog line
input buffers LINEINA and LINEINB.
MIC1
MIC2 B1
C1 G8
E9
Microphone Inputs 1 and 2 (Input) . The handset (MIC1) and headset (MIC2) microphone signal
inputs. The full-scale level is specified in the Analog Input Characteristics specification table.
MIC1_REF
MIC2_REF C2
D2 F8
E8 Microphone Inputs 1 and 2 Pseudodifferential References (Input) . Ground references for the
microphone inputs MIC1 and MIC2.
MIC1_BIAS
MIC2_BIAS E3
E2 H7
H8
Microphone Bias Voltages 1 and 2 (Output) . Bias voltage for the microphones MIC1 and MIC2.
MIC2_SDET F2 H6
Microphone 2 Short Detect (Input) . Transitions on this input can be configured to cause
interrupts that represent the pressing and releasing of a button that shorts the headset
microphone to ground.
DMIC_SCLK B3 B7 Digital Mic Serial Clock (Output) . The high-speed clock output to the digital microphone(s).
DMIC_SD C4 A8 Digital Mic Serial Data (Input) . The serialized data input from the digital microphone(s).
XSP_SCLK A4 A6 Auxiliary Serial Port (XSP), Serial Clock (Input/Output) . Serial shift clock for the interface.
XSP_LRCK C5 A7
XSP, Left/Right Clock (Input/Output) . Identifies the start of each serialized PCM data word. When
the I²S interface format is selected, this signal also indicates which channel, Left or Right, is
currently active on the serial PCM audio data lines.
XSP_SDIN A5 B5 XSP, Data Input (Input) . Input for two’s complement serial PCM audio data.
XSP_SDOUT B4 B6 XSP, Data Output (Output) . Output for two’s complement serial PCM audio data.
ASP_SCLK C6 B4 Audio Serial Port (ASP), Serial Clock (Input/Output) . Serial shift clock for the interface.
ASP_LRCK B5 A5
ASP, Left/Right Clock (Input/Output) . Identifies the start of each serialized PCM data word and
indicates which channel, Left or Right, is currently active on the serial PCM audio data lines.
ASP_SDIN A7 A3 ASP, Data Input (Input) . Input for two’s complement serial PCM audio data.
ASP_SDOUT B6 A4 ASP, Data Output (Output) . Output for two’s complement serial PCM audio data.
VSP_SCLK D7 C2 Voice Serial Port (VSP), Serial Clock (Input/Output) . Serial shift clock for the interface.
VSP_LRCK D8 D1
Voice Serial Port, Left/Right Clock (Input/Output) . Identifies the start of each serialized PCM
data word. When the I²S interface format is selected, this signal also indicates which channel, Left
or Right, is currently active on the serial PCM audio data lines.
VSP_SDIN C8 B1 VSP, Data Input (Input) . Input for two’s complement serial PCM audio data.
VSP_SDOUT C7 C1 VSP, Data Output (Output) . Output for two’s complement serial PCM audio data.
HPOUTA
HPOUTB H7
H6 J1
J2 Headphone Audio Output (Output) . The full-scale output level is specified in the HP Output
Characteristics specification table.
HPOUT_REF G6 H2
Pseudodifferential Headphone Output Reference (Input) . Ground reference for the headphone
amplifiers.