Cirrus Logic CS42L73 - Manual (Page 6)

6 DS882F1
CS42L73
6.8.4 Short Detect Automatic Mute Control .................................................................................... 86
6.9 Digital Mic and Master Clock Control (Address 0Bh) ..................................................................... 87
6.9.1 Digital Mic Shift Clock Divide Ratio ....................................................................................... 87
6.9.2 Master Clock Source Selection ............................................................................................. 87
6.9.3 Master Clock Divide Ratio ..................................................................................................... 87
6.9.4 Master Clock Disable ............................................................................................................ 87
6.10 XSP Control (Address 0Ch) ......................................................................................................... 88
6.10.1 Tristate XSP Interface ......................................................................................................... 88
6.10.2 XSP Digital Interface Format ............................................................................................... 88
6.10.3 XSP PCM Interface Mode ................................................................................................... 88
6.10.4 XSP PCM Format Bit Order ................................................................................................ 88
6.10.5 XSP SCLK Source Equals MCLK ....................................................................................... 88
6.11 XSP Master Mode Clocking Control (Address 0Dh) .................................................................... 89
6.11.1 XSP Master/Slave Mode ..................................................................................................... 89
6.11.2 XSP Master Mode Clock Control Dividers ........................................................................... 89
6.12 ASP Control (Address 0Eh) ......................................................................................................... 89
6.12.1 Tristate ASP Interface ......................................................................................................... 89
6.12.2 ASP Sample Rate ............................................................................................................... 90
6.12.3 ASP SCLK Source Equals MCLK ....................................................................................... 90
6.13 ASP Master Mode Clocking Control (Address 0Fh) ..................................................................... 90
6.13.1 ASP Master/Slave Mode ..................................................................................................... 90
6.13.2 ASP Master Mode Clock Control Dividers ........................................................................... 90
6.14 VSP Control (Address 10h) .......................................................................................................... 91
6.14.1 Tristate VSP Interface ......................................................................................................... 91
6.14.2 VSP Digital Interface Format ............................................................................................... 91
6.14.3 VSP PCM Interface Mode ................................................................................................... 91
6.14.4 VSP PCM Format Bit Order ................................................................................................ 91
6.14.5 VSP SDIN Location ............................................................................................................. 92
6.14.6 VSP SCLK Source Equals MCLK ....................................................................................... 92
6.15 VSP Master Mode Clocking Control (Address 11h) ..................................................................... 92
6.15.1 VSP Master/Slave Mode ..................................................................................................... 92
6.15.2 VSP Master Mode Clock Control Dividers ........................................................................... 92
6.16 VSP and XSP Sample Rate (Address 12h) ................................................................................. 93
6.16.1 VSP Sample Rate ............................................................................................................... 93
6.16.2 XSP Sample Rate ............................................................................................................... 93
6.17 Miscellaneous Input and Output Path Control (Address 13h) ...................................................... 94
6.17.1 Digital Swap/Mono .............................................................................................................. 94
6.17.2 Input Path Channel B=A ...................................................................................................... 94
6.17.3 PREAMP and PGA Channel B=A ....................................................................................... 94
6.17.4 PGA Soft-Ramp ................................................................................................................... 95
6.17.5 Analog Zero Cross .............................................................................................................. 95
6.17.6 Digital Soft-Ramp ................................................................................................................ 96
6.17.7 Analog Output Soft Ramp ................................................................................................... 96
6.18 ADC/Input Path Control (Address 14h) ........................................................................................ 97
6.18.1 PGA x Input Select .............................................................................................................. 97
6.18.2 Boost x ................................................................................................................................ 97
6.18.3 Invert ADCx Signal Polarity ................................................................................................. 97
6.18.4 Input Path x Digital Mute ..................................................................................................... 97
6.19 Mic PreAmp and PGA Volume Control: Channel A (Mic 1, Address 15h) and Channel B
(Mic 2, Address 16h) .......................................................................................................................... 98
6.19.1 Mic PREAMP x Volume ....................................................................................................... 98
6.19.2 PGAx Volume ...................................................................................................................... 98
6.20 Input Path x Digital Volume Control: Channel A (Address 17h) and B (Address 18h) ................. 99
6.20.1 Input Path x Digital Volume Control .................................................................................... 99