Cirrus Logic CS42L73 - Manual (Page 16)

16 DS882F1
CS42L73
1.4 Digital Pin/Ball I/O Configurations
Notes:
• All outputs are disabled when RESET is active.
• Internal weak pull up/down minimum and typical resistances are 550 k  and 1 M
• Typical hysteresis is 500 mV within the 650 mV to 1.15 V window.
• The xSP_SCLK, xSP_LRCK, and xSP_SDOUT (x = X, A, or V) outputs may be disabled via register controls as
described in sections
“High-impedance Mode” on page 52 and “Master and Slave Timing” on page 52 .
• Refer to specification table “Digital Interface Specifications and Characteristics” on page 35 for details on the digital
I/O DC characteristics (output voltages/load-capacity, input switching threshold voltages, etc.). Inputs without inte-
grated pull-ups/downs must not be left floating. All inputs must be driven or pulled (internally and/or externally) to a
valid high or low level, as defined in the specification table.
• Refer to specification tables “Switching Specifications—Serial Ports—I²S Format” on page 38 on page 47 , “Switch-
ing Specifications—Serial Ports—PCM Format” on page 39 , and “Switching Specifications—Control Port” on
page 40 for digital I/O AC characteristics (timing specifications).
• I/O voltage levels must not exceed the I/O’s corresponding power supply voltage. I/O voltage levels must not exceed
the voltage listed in
“Absolute Maximum Ratings” on page 20 .
Power
Supply I/O Name Direction
Internal
Connections Configuration
VL MCLK1 Input Weak Pull-down Hysteresis on CMOS Input
MCLK2 Input Weak Pull-down Hysteresis on CMOS Input
RESET Input - Hysteresis on CMOS Input
SCL Input - Hysteresis on CMOS Input
SDA Input/Output -
Hysteresis on CMOS Input/
CMOS Open-drain Output
INT Output Weak Pull-up CMOS Open-drain Output
XSP_SCLK Input/Output Weak Pull-down Hysteresis on CMOS Input/CMOS Output
XSP_LRCK Input/Output Weak Pull-down Hysteresis on CMOS Input/CMOS Output
XSP_SDIN Input Weak Pull-down Hysteresis on CMOS Input
XSP_SDOUT Output Weak Pull-down Tristateable CMOS Output
ASP_SCLK Input/Output Weak Pull-down
Hysteresis on CMOS Input/
CMOS Output
ASP_LRCK Input/Output Weak Pull-down Hysteresis on CMOS Input/CMOS Output
ASP_SDIN Input Weak Pull-down Hysteresis on CMOS Input
ASP_SDOUT Output Weak Pull-down Tristateable CMOS Output
VSP_SCLK Input/Output Weak Pull-down Hysteresis on CMOS Input/CMOS Output
VSP_LRCK Input/Output Weak Pull-down Hysteresis on CMOS Input/CMOS Output
VSP_SDIN Input Weak Pull-down Hysteresis on CMOS Input
VSP_SDOUT Output Weak Pull-down Tristateable CMOS Output
DMIC_SCLK Output - CMOS Output
DMIC_SD Input Weak Pull-down Hysteresis on CMOS Input