Cirrus Logic CS42L73 - Manual (Page 88)

88 DS882F1
CS42L73
6.10 XSP Control (Address 0Ch)
6.10.1 Tristate XSP Interface
Determines the state of the XSP drivers.
Note: Slave/Master Mode is determined by the XSP Master/Slave Mode bit described on page 89 .
6.10.2 XSP Digital Interface Format
Configures the XSP digital interface format.
6.10.3 XSP PCM Interface Mode
Applicable only if XSPDIF = 1b (PCM Format). Configures the XSP PCM interface mode.
6.10.4 XSP PCM Format Bit Order
Applicable only if XSPDIF = 1b (PCM Format). Configures the order in which the bits are transmitted on
XSP_SDOUT and received on XSP_SDIN.
6.10.5 XSP SCLK Source Equals MCLK
Applicable only if XSPDIF = 0b (I²S Format) and X_M/S = 1b (Master Mode). Configures the XSP_SCLK
signal source and speed.
7 6 5 4 3 2 1 0
3ST_XSP XSPDIF X_PCM_MODE1 X_PCM_MODE0 X_PCM_BIT_
ORDER
Reserved X_SCK=MCK1 X_SCK=MCK0
3ST_XSP
XSP State
Slave Mode
Master Mode
0 Serial port clocks are inputs and SDOUT is output Serial port clocks and SDOUT are outputs
1 Serial port clocks are inputs and SDOUT is HI-Z Serial port clocks and SDOUT are HI-Z
Application: Refer to section “High-impedance Mode” on page 52 .
XSPDIF XSP Interface Format
0 I²S
1 PCM (must also set X_PCM_MODE[1:0] and X_PCM_BIT_ORDER)
Application: Refer to section “Formats” on page 54 .
X_PCM_MODE[1:0] XSP PCM Interface Mode
00 Mode 0
01 Mode 1
10 Mode 2
11 Reserved
Application: Refer to section “PCM Format” on page 55 .
X_PCM_BIT_ORDER XSP_SDOUT/XSP_SDIN Bit Order
0 MSB to LSB
1 LSB to MSB
Application: Refer to section “PCM Format” on page 55 .
X_SCK=MCK[1:0] Output XSP_SCLK Sourcing Mode
00 SCLK  MCLK (SCLK = ~64 • Fs) Mode
01 Reserved
10 SCLK = MCLK Mode
11 SCLK = Pre-MCLK Mode
Application: Refer to section “SCLK = MCLK Modes” on page 53 .