Cirrus Logic CS42L73 - Manual (Page 8)

8 DS882F1
CS42L73
6.39.1 Limiter Maximum Threshold ESL [B] ................................................................................. 112
6.39.2 Limiter Cushion Threshold ESL [B] ................................................................................... 112
6.40 ALC Enable and Attack Rate AB (Address 2Fh) ........................................................................ 113
6.40.1 ALC for Channels A and B (ALCx) .................................................................................... 113
6.40.2 ALC Attack Rate for Channels A and B ............................................................................. 113
6.41 ALC Release Rate AB (Address 30h) ........................................................................................ 113
6.41.1 ALC Release Rate for Channels A and B ......................................................................... 113
6.42 ALC Threshold AB (Address 31h) .............................................................................................. 114
6.42.1 ALC Maximum Threshold for Channels A and B ............................................................... 114
6.42.2 ALC Minimum Threshold for Channels A and B ................................................................ 114
6.43 Noise Gate Control AB (Address 32h) ....................................................................................... 115
6.43.1 Noise Gate Enable for Channels A and B (NGx) .............................................................. 115
6.43.2 Noise gate Threshold and Boost for Channels A and B .................................................... 115
6.43.3 Noise Gate Delay Timing for Channels A and B ............................................................... 115
6.44 ALC and Noise Gate Misc Control (Address 33h) ..................................................................... 116
6.44.1 ALC Ganging of Channels A and B ................................................................................... 116
6.44.2 Noise Gate Ganging of Channels A and B ........................................................................ 116
6.44.3 ALCx Soft-Ramp Disable .................................................................................................. 116
6.44.4 ALCx Zero Cross Disable .................................................................................................. 116
6.45 Mixer Control (Address 34h) ..................................................................................................... 117
6.45.1 VSP Mixer Output Stereo .................................................................................................. 117
6.45.2 XSP Mixer Output Stereo .................................................................................................. 117
6.45.3 Mixer Soft-Ramp Enable ................................................................................................... 117
6.45.4 Mixer Soft-Ramp Step Size/Period .................................................................................... 117
6.46 Stereo Mixer Input Attenuation (Addresses 35h through 54h) ................................................... 118
6.46.1 Stereo Mixer Input Attenuation .......................................................................................... 119
6.47 Mono Mixer Controls (Address 55h) .......................................................................................... 120
6.47.1 Speakerphone (SPK) Mixer, ASP Select .......................................................................... 120
6.47.2 Speakerphone (SPK) Mixer, XSP Select .......................................................................... 120
6.47.3 Ear Speaker/Speakerphone Line Output (ESL) Mixer, ASP Select .................................. 120
6.47.4 ESL Mixer, Auxiliary Serial Port (XSP) Select ................................................................... 120
6.48 Mono Mixer Input Attenuation (Addresses 56h through 5Dh) .................................................... 121
6.48.1 Mono Mixer Input Attenuation ........................................................................................... 121
6.49 Interrupt Mask Register 1 (Address 5Eh) ................................................................................... 122
6.50 Interrupt Mask Register 2 (Address 5Fh) ................................................................................... 122
6.51 Interrupt Status Register 1 (Address 60h) ................................................................................. 122
6.51.1 MIC2 Short Detect ............................................................................................................. 122
6.51.2 Thermal Overload Detect .................................................................................................. 122
6.51.3 Digital Mixer Overflow ....................................................................................................... 123
6.51.4 Input Path x Overflow ........................................................................................................ 123
6.52 Interrupt Status Register 2 (Address 61h) ................................................................................. 123
6.52.1 Voice ASRC Data Out Lock .............................................................................................. 123
6.52.2 Voice ASRC Data In Lock ................................................................................................. 123
6.52.3 Audio ASRC Data Out Lock .............................................................................................. 124
6.52.4 Audio ASRC Data In Lock ................................................................................................. 124
6.52.5 Auxiliary ASRC Data Out Lock .......................................................................................... 124
6.52.6 Auxiliary ASRC Data In Lock ............................................................................................. 124
6.53 Fast Mode 1 (Address 7Eh) ....................................................................................................... 125
6.53.1 Fast Mode Bits 15:8 .......................................................................................................... 125
6.54 Fast Mode 2 (Address 7Fh) ....................................................................................................... 125
6.54.1 Fast Mode Bits 7:0 ............................................................................................................ 125
7. PCB LAYOUT CONSIDERATIONS ................................................................................................... 125
7.1 Power Supply ............................................................................................................................... 125
7.2 Grounding .................................................................................................................................... 125