Cirrus Logic CS42L73 - Manual (Page 87)

DS882F1 87
CS42L73
6.9 Digital Mic and Master Clock Control (Address 0Bh)
6.9.1 Digital Mic Shift Clock Divide Ratio
Sets the divide ratio between the internal Master Clock (MCLK) and the digital mic interface shift clock
output.
Note: Refer to section “Digital Microphone (DMIC) Interface” on page 60 for a listing of the supported
digital mic Interface shift clock rates and their associated programming settings.
6.9.2 Master Clock Source Selection
Selects the clock source for internal converters and core Master Clock (internal MCLK).
6.9.3 Master Clock Divide Ratio
Selects the divide ratio between the selected MCLK source and the internal MCLK.
Note: Refer to section “Internal Master Clock Generation” on page 42 for a listing of the supported
MCLK rates and their associated programming settings.
6.9.4 Master Clock Disable
Configures the state of the internal MCLK signal prior to its fanout to all internal circuitry.
7 6 5 4 3 2 1 0
DMIC_SCLK_
DIV
Reserved Reserved MCLKSEL MCLKDIV2 MCLKDIV1 MCLKDIV0 MCLKDIS
DMIC_SCLK_DIV DMIC_SCLK Divide Ratio (from MCLK)
0
/2
1 /4
MCLKSEL Internal MCLK source
0 MCLK1
1 MCLK2
MCLKDIV[2:0] MCLK Divide Ratio (from MCLK1 or MCLK2 Input)
000 Divide by 1
001 Reserved
010 Divide by 2
011 Divide by 3
100 Divide by 4
101 Divide by 6
110 to 111 Reserved
MCLKDIS MCLK signal into CODEC
0 On
1 Off; Disables the clock tree to save power when the CODEC is powered down.