Cirrus Logic CS42L73 - Manual (Page 65)

DS882F1 65
CS42L73
4.11.5 Mixer Attenuation Values
The digital mixer contains fixed attenuation blocks and programmable attenuation blocks. The attenuation
values associated with these blocks are as described in
Figure 32 or in the related control register de-
scriptions, except for one caveat. The caveat is the result of the binary math of the mixer circuit and design
intent. For all settings other than 0 dB, the actual attenuation on the mixer input is a little more than the
rounded-to-integer number listed in the register description. These small offsets increase with larger
amounts of attenuation. At the largest attenuation setting, -62 dB, the applied attenuation is actually
-62.216 dB.
The benefits of the offsets are twofold and relate to how premixer attenuation is applied (refer to the
“Avoiding Mixer Clipping” section on page 64 ). First, for commonly used -6n dB (n 1, 2, etc.}) attenua-
tion settings, the offset rounds the attenuation to exactly the desired 1/2
n
factor (e.g., 20Log(1/2) = 6.021
dB, not 6.000 dB). Secondly, for attenuation settings other than -6n dB, the always positive offset provides
slightly more attenuation, yielding some margin to ensure that mixer clipping is avoided.
4.12 Recommended Operating Procedures
The following sections describe the recommended power-up and power-down sequences for typical use
cases. Implement these to minimize audible artifacts and to provide the best-possible user experience.
4.12.1 Initial Power-Up Sequence
The initial power-up sequence must be executed whenever power is applied to the CS42L73 from a pow-
ered-down state, or if there is a known or suspected disturbance on the power supply that brings it below
the
“Recommended Operating Conditions” on page 19 .
1. Hold RESET low (active) until all the power supply rails have risen to greater than or equal to the
minimum recommended operating voltages.
– Ensure the ramping-up of each of the supplies is smooth (no down-slope regions) and does not
take longer than the specified time ( t
pwr-rud
).
– The last power supply rail to reach its operating voltage must do so within the specified time (t
pwr-rs
)
from when the first power rail reaches its operating voltage. Exception: the VP supply may be
applied or removed independently of RESET and the other power rails (except for the VA supply,
see
(Note 4) ).
2. Continue to hold RESET low for at least the specified hold time (t
rh(PWR-RH)
) after power supplies
reach their operating voltage.
3. Bring RESET high.
4. Wait the specified minimum time (t
ris
) following RESET going high before using the control port.
Refer to the specifications on page 36 , page 40 , and Figure 10 on page 36 to find the durations referenced
in this power-up sequence.
Note: A valid MCLK signal is not required to be present to communicate with the control port, however
changes made to the control port will not take effect until a valid MCLK signal is present. An MCLK
Referenced Control Register Location
XSPO_STEREO .................
VSPO_STEREO .................
MXR_SFTR_EN..................
MXR_STEP[2:0]..................
“Stereo *_A[5:0]” .................
ESL_ASP_SEL[1:0] ............
ESL_XSP_SEL[1:0] ............
SPK_ASP_SEL[1:0]............
SPK_XSP_SEL[1:0]............
“Mono *_A[5:0]”................... “XSP Mixer Output Stereo” on page 117
“VSP Mixer Output Stereo” on page 117
“Mixer Soft-Ramp Enable” on page 117
“Mixer Soft-Ramp Step Size/Period” on page 117
“Stereo Mixer Input Attenuation” on page 119
“Ear Speaker/Speakerphone Line Output (ESL) Mixer, ASP Select” on page 120
“ESL Mixer, Auxiliary Serial Port (XSP) Select” on page 120
“Speakerphone (SPK) Mixer, ASP Select” on page 120
“Speakerphone (SPK) Mixer, XSP Select” on page 120
“Mono Mixer Input Attenuation” on page 121