AMETEK BPS Series Programming Manual - Manual (Page 169)

BPS / MX / RS Series SCPI Programming Manual AMETEK Programmable Power
Manual P/N 7003-961 Rev. AA 169
7.4 Standard Event Status Group
This group consists of an Event register and an Enable register that are programmed by
Common commands. The Standard Event register latches events relating to the interface
communication status (see Figure 7-1). It is a read-only register that is cleared when read.
The Standard Event Enable register functions similarly to the enable registers of the
Operation and Questionable status groups.
Command Action
*ESE programs specific bits in the Standard Event Enable register.
*ESR? reads and clears the Standard Event Event register.
The PON bit in the Standard Event Event register is set whenever the AC source is turned
on. The most common use for PON is to generate an SRQ at power-on following an
unexpected loss of power.
7.5 Status Byte Register
This register summarizes the information from all other status groups as defined in the IEEE
488.2 Standard Digital Interface for Programmable Instrumentation. The bit configuration is
shown in Table 7-2.
Command Action
*STB? reads the data in the register but does not clear it (returns MSS in bit 6)
serial poll reads and clears the data in the register (returns RQS in bit 6)
The MSS Bit
This is a real-time (unlatched) summary of all Status Byte register bits that are enabled by
the Service Request Enable register. MSS is set whenever the AC source has one or more
reasons for requesting service. *STB? reads the MSS in bit position 6 of the response but
does not clear any of the bits in the Status Byte register.
The RQS Bit
The RQS bit is a latched version of the MSS bit. Whenever the AC source requests service,
it sets the SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register.
When the controller does a serial poll, RQS is cleared inside the register and returned in bit
position 6 of the response. The remaining bits of the Status Byte register are not disturbed.
The MAV bit and Output Queue
The Output Queue is a first-in, first-out (FIFO) data register that stores AC source-to-
controller messages until the controller reads them. Whenever the queue holds one or more
bytes, it sets the MAV bit (bit 4) of the Status byte register.