Altera ALTDLL - Manual (Page 10)

Chapter 2: Getting Started 2–4
Design Example: Implementing Read Paths Using Stratix III Devices
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
The timing analyzer reports margins on the following paths:
■ Address and command setup and hold margin
■ Half-rate address and command setup and hold margin
■ Core setup and hold margin
■ Core reset and removal setup and hold margin
■ Write setup and hold margin
■ Read capture setup and hold margin
f For more information about timing analysis and reporting using the ALTDLL and
ALTDQ_DQS external memory solution, refer to the
Analyzing Timing of Memory IP
chapter in volume 2 of the External Memory Interface Handbook.
Adjust Constraints
The timing report shows the worst case setup and hold margin for the different paths
in your design. If the setup and hold margin do not meet timing requirements, adjust
the phase setting of the clocks that latch the data.
For example, the address and command outputs are clocked by an address and
command clock that may be different than the system clock, which is 0°. The system
clock clocks the clock outputs going to the memory. If the report timing script
indicates that using the default phase setting for the address and command clock
results in more hold time than setup time, adjust the address and command clock to
be less negative than the default phase setting to ensure that there is less hold margin.
Similarly, adjust the address and command clock to be more negative than the default
phase setting if there is more setup margin.
Design Example: Implementing Read Paths Using Stratix III Devices
This section provides a walkthrough of a simple design example. The design example
demonstrates a Stratix III device reading from an external DDR2 SDRAM. The DDR2
external memory interface is implemented using the ALTDLL and ALTDQ_DQS
megafunctions. This design requires 1 DQS and 8 DQ input pins. The DQS frequency
for the design is 150 MHz and the data rate is 300 Mbps.
1 For a more complex design example, refer to “Design Example: Implementing
Half-Rate DDR2 Interface in Stratix III Devices” on page 4–49 .
f
The design examples are available next to the ALTDLL and ALTDQ_DQS
Megafunctions User Guide on the
Documentation: User Guides page of the Altera
website.