Altera ALTDLL - Manual (Page 74)

Chapter 4: Functional Description 4–38
ALTDQ_DQS Megafunction Ports
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
DQ Input Path Megafunction Ports
Table 4–15 summarizes all the ports on the megafunction that configure the DQ input
path. The possible values for <IO> are BIDIR_DQ and INPUT_DQ .
oct_reg_clk Input Optional GND This port feeds the full-rate clock signal to the
<IO>
_OCT_FF:clk and <IO> _OCT_DDIO_OE:clk
ports.
output_dq_hr_oct_in
[2*n
o
-1..0]
Input Optional GND This port feeds the half-rate output DQ signal for the
OUTPUT_DQ_OCT_HR_DDIO_OUT:datainhi /
datainlo ports.
output_dq_oct_in
[n
o
-1..0]
Input Optional GND This port feeds the full-rate output DQ signal for the
OUTPUT_DQ_OCT_FF:d ,
OUTPUT_DQ_OCT_DDIO_OE:oe ,
OUTPUT_DQ_OCT_DELAY_CHAIN1:datain ,
OUTPUT_DQ_OCT_DELAY_CHAIN2:datain , or
output_dq_oct_out port.
output_dq_oct_out
[n
o
-1..0]
Output Optional — This port outputs signal from the
OUTPUT_DQ_OCT_DELAY_CHAIN2:dataout ,
OUTPUT_DQ_OCT_DELAY_CHAIN1:dataout ,
OUTPUT_DQ_OCT_FF:q ,
OUTPUT_DQ_OCT_DDIO_OE:dataout , or
output_dq_oct_in port.
Table 4–14. Megafunction Ports to Configure OCT Path (Part 2 of 2)
Port Name Type
Optional/
Required
Default Description
Table 4–15. Megafunction Ports to Configure DQ Input Path (Part 1 of 2)
Port Name Type
Optional/
Required
Default Description
bidir_dq_areset
[n
b
-1..0]
Input Optional GND This port is connected to all areset port in the
bidirectional DQ IO primitives that is used to
asynchronously reset the registers in those
primitives.
bidir_dq_hr_input_
data_out[4*n
b
-1..0]
Output Optional — This port outputs the half-rate DDR bidirectional DQ
signal from the
BIDIR_DQ_HALF_RATE_INPUT:dataout
port.
bidir_dq_input_data_in
[n
b
-1..0]
Input Optional GND This port feeds the bidirectional DQ signal for the
BIDIR_DQ_INPUT_DELAY_CHAIN:datain ,
BIDIR_DQ_INPUT_FF:d ,
BIDIR_DQ_DDIO_IN:datain , or
bidir_dq_input_data_out port.
bidir_dq_input_data_ou
t_high[n
b
-1..0]
Output Optional — This port outputs the full-rate DDR bidirectional DQ
signal (rising edge) from the
BIDIR_DQ_IPA_HIGH:dataout or
BIDIR_DQ_DDIO_IN:regouthi .
bidir_dq_input_data_ou
t_low[n
b
-1..0]
Output Optional — This port outputs the full-rate DDR bidirectional DQ
signal (falling edge) from the
BIDIR_DQ_IPA_LOW:dataout or
BIDIR_DQ_DDIO_IN:regoutlo .