Altera ALTDLL - Manual (Page 109)

A–8 Appendix A: Clear Box Generator
Clear Box Generator Options
ALTDLL and ALTDQ_DQS Megafunctions User Guide © February 2012 Altera Corporation
DQS_CTRL_LATCHES_ENABLE Optional FALSE FALSE, TRUE This parameter describes whether the
delayctrlin[5..0] and
offsetctrlin[5..0] inputs are
latched or not. If set to TRUE , only a
DLL feeds the
delayctrlin[5..0] input bus.
USE_DQS_ENABLE_CTRL_PHASE
_CTRLIN
Optional TRUE FALSE, TRUE If set to TRUE , the phase setting is
determined by the phasectrlin
input. If set to FALSE , the phase
setting is determined by the
<phase_setting> parameter.
DQS_ENABLE_CTRL_PHASE_
SETTING
Optional 0 0..7 This parameter determines the phase
shift implemented by the delay chain if
<use_phasectrlin> is set to
FALSE ;
otherwise, you can ignore this setting.
LEVEL_DQS_ENABLE OptionalO FALSE FALSE, TRUE This is an optional field and defaults to
FALSE .
DELAY_DQS_ENABLE_BY_HALF_
CYCLE
Optional FALSE FALSE, TRUE This is an optional field and defaults to
FALSE .
DQS_ENABLE_CTRL_ADD_PHASE
_TRANSFER_REG
Optional FALSE FALSE, TRUE,
DYNAMIC If set to TRUE , a negative
edge-triggered register is added in data
path for the clock phase transfer. If set
to
FALSE , no register is added. If it is
set to DYNAMIC , the
enaphasetransferreg input
determines whether the register is
added or not. You can use the
negative-edge register to guarantee the
setup and hold time for a phase
transfer.
DQS_ENABLE_CTRL_INVERT_
PHASE
Optional FALSE FALSE, TRUE,
DYNAMIC If set to TRUE , the phase output is
inverted. If set to FALSE , the phase
output is not inverted. If it is set to
DYNAMIC , the phaseinvertctrl
input determines whether the inverter
is used or not. Use the inverter to
increase the number of available
phases.
USE_IO_CLOCK_DIVIDER_
PHASECTRLIN
Optional TRUE FALSE, TRUE If set to TRUE , the phase setting is
determined by the phasectrlin
input. If set to FALSE , the phase
setting is determined by the
<phase_setting> parameter.
IO_CLOCK_DIVIDER_PHASE_
SETTING
Optional 0 0..7 This parameter determines the phase
shift implemented by the delay chain if
<use_phasectrlin> is set to
FALSE ;
otherwise, ignore this setting.
Table A–3. Megafunction Parameters to Configure DQS Input Path (Part 3 of 4)
Parameter Name
Optional/
Required Default Legal Values Description