Dqs output path megafunction ports, Dqs output path megafunction ports –35 – Altera ALTDLL User Manual

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4–35

Chapter 4: Functional Description

ALTDQ_DQS Megafunction Ports

ALTDLL and ALTDQ_DQS Megafunctions User Guide

© February 2012

Altera Corporation

DQS Output Path Megafunction Ports

Table 4–12

summarizes all the ports on the megafunction that configure the DQS

output path.

Table 4–12. Megafunction Ports to Configure DQS Output Path

Port Name

Type

Optional/

Required

Default

Description

dqs_areset

Input

Optional

GND

This port is connected to the

DQS_OUTPUT_FF:clrn

,

DQS_OUTPUT_DDIO_OUT:areset

, and

DQS_OUTPUT_HR_DDIO_OUT_HIGH/_LOW:ares

et

ports that is used to asynchronously reset all

registers in those blocks.

dqs_hr_output_data_

in[3..0]

Input

Optional

GND

This port feeds the half-rate data to the

DQS_OUTPUT_HR_DDIO_OUT_HIGH:datainhi

/

datainlo

and

DQS_OUTPUT_HR_DDIO_OUT_LOW:datainhi

/

datainlo

ports.

dqs_hr_output_reg_clk

Input

Optional

GND

This port feeds the clock signal for the

DQS_OUTPUT_HR_DDIO_OUT_HIGH:clkh

/

clklo

/

muxsel

and

DQS_OUTPUT_HR_DDIO_OUT_LOW:clkhi

/

clklo

/

muxsel

ports.

dqs_output_data_in

Input

Optional

GND

This port feeds the

DQS_OUTPUT_FF:d

,

DQS_OUTPUT_DELAY_CHAIN1:datain

,

DQS_OUTPUT_DELAY_CHAIN2:datain

, or

dqs_output_data_out

port.

dqs_output_data_in_

high

Input

Optional

GND

This port feeds the

DQS_OUTPUT_DDIO_OUT:datainhi

port that is

the full-rate data for the rising edge.

dqs_output_data_in_low

Input

Optional

GND

This port feeds the

DQS_OUTPUT_DDIO_OUT:datainlo

port that is

the full-rate data for the falling edge.

dqs_output_data_out

Output

Optional

This port can be driven by the

DQS_OUTPUT_DELAY_CHAIN2:dataout

,

DQS_OUTPUT_DELAY_CHAIN1:dataout

,

DQS_OUTPUT_FF:q

,

DQS_OUTPUT_DDIO_OUT:dataout

, or

dqs_output_data_in

port.

dqs_output_reg_clk

Input

Optional

GND

This port is connected to the

DQS_OUTPUT_FF:clk

and the

DQS_OUTPUT_DDIO_OUT:clkhi

/

clklo

/

muxsel

ports that is used to clock the registers in those blocks.

dqs_output_reg_clkena

Input

Optional

V

CC

This port is connected to the

DQS_OUTPUT_FF:ena

and the

DQS_OUTPUT_DDIO_OUT:ena

ports that is

used as output enable for the registers in those block.

dqs_sreset

Input

Optional

GND

This port is connected to the

DQS_OUTPUT_FF:sclr

and

DQS_OUTPUT_DDIO_OUT:sreset

ports that is

used to synchronously reset all registers in those blocks.

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