Altera ALTDLL - Manual (Page 98)

Chapter 4: Functional Description 4–62
Design Example: Implementing Half-Rate DDR2 Interface in Stratix III Devices
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
14. The dqs_hr_output_data_in[3:0] , dqs_hr_output_data_in[3] and
dqs_hr_output_data_in[2] signals are toggled with a constant value of 1’b1.
After that, the dqs_hr_output_data_in[1] and
dqs_hr_output_data_in[0] signals are toggled with a constant value of 1’b0.
The signals are toggled at a constant rate to generate the necessary DQS write
strobe/clock signals, which are sent together with the DQ write data to the external
memory.
15. As the throughput of the data is sent at 666.666 Mbps, the DQS write strobe/clock
signal is a 333.333-MHz DDR clock signal. To obtain such a signal, the
dqs_hr_output_data_in[3] and dqs_hr_output_data_in[2] signals go
through a DDIO_OUT port, which is clocked at 166.666 MHz by the c3 PLL clock
output. At the same time, the
dqs_hr_output_data_in[1] and
dqs_hr_output_data_in[0] signals go through another DDIO_OUT port,
which is clocked at 166.666 MHz by the c3 PLL clock output.
16. Both outputs (dqs_output_hr_ddio_out_high_inst/dataout and
dqs_output_hr_ddio_out_low_inst/dataout ) of the previous DDIO_OUT
ports are channeled into another DDIO_OUT port, which is clocked at 333.333 MHz
by the c1 PLL clock output.
17. The output dqs_output_ddio_out_inst / dataout is then connected to
output_delay_chain_1 . The output
dqs_output_delay_chain1_inst / dataout is connected to
output_delay_chain_2.
18. The output dqs_output_delay_chain2_inst / dataout is connected to the
dqs_io pin, which acts as a 333.333-MHz DQS write strobe/clock signal.
f
For details about changing the delay chain values dynamically, refer to the I/O Buffer
(ALTIOBUF) Megafunction User Guide .