Altera ALTDLL - Manual (Page 31)

Chapter 3: Parameter Settings 3–13
ALTDQ_DQS Parameter Editor
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
DQ Input Register
Options
Use DQ resync
register
— DQ_RESYNC_REG_MODE Enables the DQ resynchronization register.
Supported in Arria II GX devices only.
DQ Input Register
Options
Use DQ half rate
‘dataoutbypass’
port
— DQ_HALF_RATE_USE_
DATAOUTBYPASS
If you turn on this parameter, the dataoutbypass
input dynamically routes the directin input to the
dataout output for <IO> _HALF_RATE_INPUT
block. Using this parameter, you can bypass the half-rate
registers in <IO>
_HALF_RATE_INPUT block
dynamically during the FPGA run-time.
Not supported in Arria II GX devices.
Advanced DQ IPA
Options
DQ Input Phase
Alignment Phase
Setting
Set statically
to
or
Set
dynamically
using
configuration
registers
DQ_IPA_PHASE_
SETTING
If you turn on the Set statically to option, the phase
setting can be selected from values 0 to 7 for the delay
chains. If you turn on the Select dynamically using
configuration registers option, the phase setting is
determined by the
phasectrlin input for the delay
chains. This parameter fine-tunes the resynchronization
phase for the DQ input data. The phase settings are also
called the levelling delay chains that handle the fly-by
clock topology in DDR3 interfaces.
Advanced DQ IPA
Options
Add DQ Input
Phase Alignment
Input Cycle Delay
Always,
Never, or
Based on
configuration
registers DQ_IPA_ADD_INPUT_
CYCLE_DELAY
If you turn on Always, a single cycle delay is added to
the input path. If you turn on Never, no delay is added. If
you turn on Based on configuration registers, the
enainputcycledelaysetting input controls
whether or not a single cycle delay is added to the input
path.
Advanced DQ IPA
Options
Invert DQ Input
Phase Alignment
Phase
Always,
Never, or
Based on
configuration
registers DQ_IPA_INVERT_
PHASE
If you turn on Always, the phase output is inverted. If
you turn on Never, the phase output is not inverted. If
you turn on Based on configuration registers, the
phaseinvertctrl input determines whether or not
the inverter is used. The inverter is used to increase the
number of available phases.
Advanced DQ IPA
Options
Register DQ input
phase alignment
bypass output
— DQ_IPA_BYPASS_
OUTPUT_REGISTER
Controls the output register in the DQ input path. If you
turn on this option, the output data bypasses the output
register. If you turn off this option, then the data goes
through the output register.
Table 3–6. Options on DQ IN Page (Part 2 of 3)
Parameter Name Legal Value
Clear Box
Parameter Name Description