Altera ALTDLL - Manual (Page 37)

© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
4. Functional Description
This section describes the functionality of the various blocks and ports in the ALTDLL
and ALTDQ_DQS megafunctions. This section also describes the use of delay chains
to achieve better timing margins. This section also includes an implementation
example showing these megafunctions in a custom external memory interface.
Custom External Memory Interface Datapaths Overview
This section describes the functionality of the various blocks in the external memory
datapaths that the megafunctions control.
Figure 4–1 shows the mapping of the ALTDLL and ALTDQ_DQS megafunctions to
the dedicated I/O element for external memory interfaces in Stratix IV devices.
.
1 The following blocks are not available in Arria II GX devices:
■ Dynamic OCT blocks
■ Half-rate blocks
■ I/O and DQS configuration blocks
Figure 4–1. Mapping of ALTDLL and ALTDQ_DQS Megafunctions to the Dedicated I/O Circuitry
FPGA
ALTPLL
Postamble Clock
DQS Input Path
ALTDLL
Resynchronization Clock
DQ Input Path
DQ Output Path
DQ Output Enable Path
DQS Output Path
DQS Output Enable Path
ALTDQ_DQS
DQ Write Clock
DQS Write Clock
Alignment Clock
DLL Clock
External Memory
DQ (Read)
DQ (Write)
DQS (Read)
DQS (Write)
ALTIOBUF
ALTIOBUF
ALTIOBUF
ALTIOBUF
DLL Delayed Clock
DQ/DQS OCT Path
DQ/DQS OCT Path
DLL