Instantiate the altiobuf megafunction – Altera ALTDLL User Manual

Page 90

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Chapter 4: Functional Description

4–54

Design Example: Implementing Half-Rate DDR2 Interface in Stratix III Devices

© February 2012

Altera Corporation

ALTDLL and ALTDQ_DQS Megafunctions User Guide

12. Click Finish. The dq_dqs_inst module (dq_dqs_inst.v) is generated.

Instantiate the ALTIOBUF Megafunction

After instantiating the ALTDLL and ALTDQ_DQS megafunctions, you must
instantiate the ALTIOBUF megafunction with the following I/O buffer settings:

1 bidirectional buffer for the differential DQS pins

1 output buffer for the output DQ pins

8 bidirectional buffers for the bidirectional DQ pins

To instantiate these three types of I/O buffers, perform the following steps:

1. In the Quartus II software, on the Tools menu, click MegaWizard Plug-In

Manager

.

2. On page 1, select Create a new custom megafunction variation. Click Next. Page

2a appears.

3. On page 2a, select or verify the configuration settings shown in

Table 4–34

. Click

Next

to advance from one page to the next.

4. On the Parameter Settings page, specify the parameters as shown in

Table 4–35

.

These parameters configure the general settings for the ALTIOBUF instance.

Create ‘output_dq_sreset’ input port

Turned off

Create ‘bidir_dq_areset’ input port

Turned on

Create ‘bidir_dq_sreset’ input port

Turned on

Create 'config_clk' input port

Turned on

Create 'config_datain' input port

Turned on

Create 'config_update' input port

Turned on

Table 4–33. Advanced Options (Reset and Config Ports) (Part 2 of 2)

Parameter

Value

Table 4–34. ALTIOBUF Configuration Settings

Settings

Value

1 bidirectional buffer for
the differential DQS pins

1 output buffer for the
output DQ pins

8 bidirectional buffers for
the bidirectional DQ pins

Which device family will you be
using?

Stratix III

Stratix III

Stratix III

Which megafunction would you like to
customize?

ALTIOBUF

ALTIOBUF

ALTIOBUF

Which type of output file do you want
to create?

Verilog HDL

Verilog HDL

Verilog HDL

What name do you want for the output
file?

dqs_iobuf_inst.v

output_dq_iobuf_inst.v

bidir_dq_iobuf_inst.v

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