Altera 50G Interlaken MegaCore Function User Manual
Page 11
• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.
OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.
Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times
out.
Specifying the 50G Interlaken IP Core Parameters and Options
The parameter editor GUI allows you to quickly configure your custom IP variation. You specify IP core
options and parameters in the Quartus II software.
The 50G Interlaken IP core is not supported in Qsys. You must use the IP Catalog accessible from the
Quartus II Tools menu.
The 50G Interlaken IP core does not support VHDL simulation models. Altera recommends that you
specify the Verilog HDL for both synthesis and simulation models.
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation
settings in a file named <your_ip>
.qsys
. Click OK.
Note: For Arria V GZ and Stratix V variations, you are prompted to specify an IP variation file type.
To generate the demonstration testbench and example design, you must select the Verilog HDL
and specify the Verilog file extension (
.v
).
3. Specify the parameters and options for your IP variation in the parameter editor, including one or
more of the following. Refer to
50G Interlaken IP Core Parameter Settings
for information about
specific IP core parameters.
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for processing the IP core files in other EDA tools.
4. For Arria 10 variations, follow these steps:
a. Click Generate HDL. The Generation dialog box appears.
b. Specify output file generation options, and then click Generate. The IP variation files generate
according to your specifications.
Note: To generate the demonstration testbench and example design, you must specify Verilog
HDL for both synthesis and simulation models.
c. Click Finish. The parameter editor adds the top-level
.qsys
file to the current project automatically.
If you are prompted to manually add the
.qsys
file to the project, click Project > Add/Remove Files
in Project to add the file.
5. For Arria V GZ and Stratix V variations, follow these steps:
2-2
Specifying the 50G Interlaken IP Core Parameters and Options
UG-01140
2015.05.04
Altera Corporation
Getting Started With the 50G Interlaken IP Core