Altera 50G Interlaken MegaCore Function - Manual (Page 63)

50G Interlaken IP Core Register Map
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2015.05.04
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The 50G Interlaken IP core control registers are 32 bits wide and are accessible to you using the
management interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications.
This table lists the registers available in the IP core. All unlisted locations are reserved.
Table 6-1: 50G Interlaken IP Core Register Map
Offset Name R/W Description
9'h0 PCS_BASE RO [31:8] – Constant “HSi” ASCII
[7:0] – version number
Despite its name, this register does not encode the hard PCS
base address.
9'h1 LANE_COUNT RO Number of lanes
9'h2
TEMP_SENSE
RO Device temperature according to the internal temperature
sensing diode.
[7:0] – the temperature in degrees Fahrenheit
[15:8] – the temperature in degrees Celsius
For example, when the temperature is 54 degrees Celsius
(130 degrees Fahrenheit), the value of the register is 0x3682.
To interpret this register value, you read 0x36 (decimal 54)
to be the temperature in degrees Celsius, and you read 0x82
(decimal 130) to be the temperature in degrees Fahrenheit.
This register is invalid in the following IP core variations:
• Variations that target an Arria 10 device
• Variations in which you turn off the hidden parameter
Include Temp Sense
9'h3
ELAPSED_SEC
RO [23:0] - Elapsed seconds since power up. The IP core
calculates this value from the management interface clock
(
mm_clk
) for diagnostic purposes. During continuous
operation, this value rolls over every 194 days.
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