Altera 50G Interlaken MegaCore Function - Manual (Page 14)

Figure 2-3: IP Core Generated Files
<your_ip >.cmp - VHDL component declaration file
<your_ip >.ppf - XML I/O pin information file
<your_ip >.qip - Lists IP synthesis files
<your_ip >.sip - Lists files for simulation
<your_ip >.v or .vhd
Top-level IP synthesis file <your_ip >.v or .vhd
Top-level simulation file
<simulator_setup_scripts >
<your_ip >.qsys - System or IP integration file
<your_ip >_bb.v - Verilog HDL black box EDA synthesis file
<your_ip >_inst.v or .vhd - Sample instantiation template
<your_ip >_generation.rpt - IP generation report
<your_ip >.debuginfo - Contains post-generation information
<your_ip >.html - Connection and memory map data
<your_ip >.bsf - Block symbol schematic
<your_ip >.spd - Combines individual simulation scripts
<your_ip >.sopcinfo - Software tool-chain integration file
<project directory>
<your_ip>
IP variation files
sim
Simulation files
synth
IP synthesis files
<EDA tool name>
Simulator scripts
ilk_core_50g_<version>
Subcore libraries
sim
Subcore
Simulation files
synth
Subcore
synthesis files
<HDL files >
<HDL files >
<your_ip> n
IP variation files
testbench
Testbench files
If you select the Verilog HDL for synthesis and simulation models, the demonstration testbench and
example design files are located in <your_ip> /ilk_core_50g_ <version> /sim/testbench .
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UG-01140
2015.05.04
Files Generated for Arria 10 Variations 2-5
Getting Started With the 50G Interlaken IP Core Altera Corporation
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