Altera 50G Interlaken MegaCore Function - Manual (Page 38)

supports your design in achieving timing closure more easily. In any case you must ensure that you hold
itx_num_valid
at the value of 0 when you are not driving data.
You can think of this interface as a FIFO write interface. When
itx_num_valid[2:0]
is nonzero, both
data and control information (including
itx_num_valid[2:0]
itself) are written to the transmit side data
interface. The
itx_ready
signal is the inverse of a hypothetical FIFO-almost-full flag. When
itx_ready
is
high, the 50G Interlaken IP Core is ready to accept data. When
itx_ready
is low, you can continue to
send data for another 6 to 8 clock cycles of
tx_usr_clk
.
Related Information
50G Interlaken IP Core In-Band Calendar Bits on Transmit Side on page 4-12
Description of in-band calendar bits on the TX user data transfer interface.
50G Interlaken IP Core In-Band Calendar Bits on Transmit Side
The
itx_calendar
input signal supports in-band flow control. It is synchronous with
tx_usr_clk
, but
does not align with the packets on the user data interface. The 50G Interlaken IP Core reads the
itx_calendar
bits and encodes them in control words (Burst control words and Idle control words)
opportunistically.
If you hold all the calendar bits at one, you indicate an XON setting for each channel. You should set the
calendar bits to 1 to indicate that the Interlaken link partner does not need to throttle the data it transfers
to this 50G Interlaken IP Core. Set this value by default if you choose not to use the in-band flow control
feature of the 50G Interlaken IP Core. If you decide to turn off any channel, you must drive the
corresponding bits of
itx_calendar
with zero (the XOFF setting) for that channel.
The50G Interlaken IP Core transmits each page of the
itx_calendar
bits on the Interlaken link in a
separate control word, starting with the most significant page and working through the pages, in order, to
the least significant page.
Consider an example where the number of calendar pages is four and itx_calendar bits are set to the value
64'h1111_2222_3333_4444. In this example, the Number of calendar pages parameter is set to four, and
therefore the width of the
itx_calendar
signal is 4 x 16 = 64 bits. Each of these bits is a calendar bit. The
transmission begins with the page with the value of 16'h1111 and works through the pages in order until
the least significant page with the value of 16'h4444.
In this example, four control words are required to send the full set of 64 calendar bits from the
itx_calendar
signal. The 50G Interlaken IP Core automatically sets the Reset Calendar bit[56] of the
next available control word to the value of one, to indicate the start of transmission of a new set of
calendar pages, and copies the most significant page (16'h1111 in this example) to the In-Band Flow
Control bits[55:40] of the control word. It maps the most significant bit of the page to the control word
bit[55] and the least significant bit of the page to the control word bit[40].
The table shows the value of the Reset Calendar bit and the In-Band Flow Control bits in the four
Interlaken link control words that transmit the 64'h1111_2222_3333_4444 value of
itx_calendar
:
Table 4-2: Value of Reset Calendar Bit and In-band Flow Control Bits in the Example
Control Word Reset Calendar Bit (bit [56]) In-Band Flow Control Bits (bits [55:40])
First 1 16'b0001000100010001 (16'h1111)
4-12 50G Interlaken IP Core In-Band Calendar Bits on Transmit Side
UG-01140
2015.05.04
Altera Corporation Functional Description
Send Feedback