Altera 50G Interlaken MegaCore Function - Manual (Page 41)

50G Interlaken IP Core Receiver Side Example
The 50G Interlaken IP Core can generate interleaved data transfers on the RX user data transfer interface.
The IP core always toggles the
irx_sob
and
irx_eob
signals to indicate the beginning of the burst and
end of the burst.
Figure 4-8: 50G Interlaken IP Core Receiver Side Example
This example illustrates the expected behavior of the 50G Interlaken IP core application interface receive
signals during data transfers from the IP core to the application on the RX user data transfer interface in
interleaved mode.
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9
rx_usr_clk
irx_sop
irx_sob
irx_eob
irx_dout_words d1
3’b100 3’b100 3’b011 3’b010 3’b100 3’b000
4’b0000 4’b0000 4’b0000 4’b0000 4’b1011 4’b1011 4’b0000
3’b100 3’b100
d2 d3 d4 d5 d6 d7
irx_num_valid
irx_eopbits
irx_chan 8’h2 8’h4 8’h4 8’h3 8’h2
The figure shows the timing diagram for an interleaved data transfer in Interleaved mode. In cycle 1, the
IP core asserts
irx_sop
and
irx_sob
, indicating that this cycle is both the start of the burst and the start
of the packet. The first word is MSB aligned at the top. The value the IP core drives on
irx_chan
indicates
the data targets channel 2. You must sample
irx_chan
during cycles in which
irx_sob
is asserted. The
irx_chan
output signal is not guaranteed to remain valid for the duration of the burst.
In cycle 2, the IP core asserts
irx_eob
, indicating the data the IP core transfers to the application in this
clock cycle is the end of the burst.
irx_num_valid[2:0]
indicates all four words are valid. However, the
data in this cycle is not end of packet data. The IP core will transfer at least one additional data burst in
this packet, possibly interleaved with one or more bursts in packets that target different data channels.
Cycle 3 is a short burst with both
irx_sob
and
irx_eob
asserted. The IP core drives the value of three on
irx_num_valid[2:0]
to indicate that three words of the four-word
irx_dout_words
data bus are valid.
The data is packed in the most significant words of
irx_dout_words
.The IP core drives the value of
4'b1011 on
irx_eopbits
to indicate that the data the IP core transfers to the application in this cycle are
the final words of the packet, and that in the final word of the packet, only three bytes are valid data. The
value the IP core drives on
irx_chan
indicates this burst targets channel 4.
In cycle 4, the
irx_num_valid[2:0]
signal has the value of zero, which means this cycle is an idle cycle.
In cycle 5, the IP core sends another single-cycle data burst to channel 2, by asserting
irx_sob
and
irx_eob
to indicate this data is both the start and end of the burst. The IP core does not assert
irx_sop
,
because this burst is not start of packet data.
irx_eopbits
has the value of 4'b0000, indicating this burst is
UG-01140
2015.05.04
50G Interlaken IP Core Receiver Side Example 4-15
Functional Description Altera Corporation
Send Feedback