B. additional information, Document revision history, Additional information – Altera 50G Interlaken MegaCore Function User Manual

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Additional Information

B

2015.05.04

UG-01140

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This section provides additional information about the document and Altera.

Document Revision History

Table B-1: 50G Interlaken MegaCore Function User Guide Revision History

Date

ACDS Version

Changes Made

2015.05

.04

15.0

• Added new TX scrambler seed parameter in new section

TX Scrambler Seed

on page 3-2. Previously this parameter was hidden (

SCRAM_CONST

) and

unavailable for Arria 10 devices. In the IP core version 15.0 and later, you

must modify the scrambler seed from the parameter editor.

• Improved description of itx_ifc_err output signal in

50G Interlaken IP Core

User Data Transfer Interface Signals

on page 5-4.

• Improved description of itx_hungry output signal in

50G Interlaken IP Core

Interlaken Link and Miscellaneous Interface Signals

on page 5-8.

• Updated filenames for hidden parameter editing to include the filenames for

Arria 10 variations, in

Modifying Hidden Parameter Values

on page 9-4.

2014.12

.15

14.1

• Updated release-specific information for the software release v14.1, including

new resource utilization numbers and new Arria 10 speed grade notation and

information. Resource utilization numbers improved by 20% in the v14.0

release.

• Updated for new Quartus II IP Catalog, which replaces the MegaWizard Plug-

In Manager starting in the Quartus II software v14.0. Changes are located

primarily in Getting Started with the 50G Interlaken IP Core chapter.

Reordered the chapter to accommodate the new descriptions.

• Corrected instructions to connect the external TX PLL to include the

tx_cal_

busy

signal, and added example figure to illustrate the required connections

between the IP core and an ATX PLL. Changes are located in Adding the

External PLL section. .

• Added information about the required wait from reset to successful register

access in IP Core Reset section. .

• Corrected width of

reconfig_waitrequest

signal to one bit. This signal has

been a single bit in all versions that support Arria 10 devices, starting with the

IP core version 13.1 Arria 10 Edition.

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