Altera 50G Interlaken MegaCore Function - Manual (Page 22)

You must connect the external PLL signals and the Arria 10 50G Interlaken IP core transceiver Tx PLL
interface signals according to the following rules:
• Connect the
tx_serial_clk
input pin for each Interlaken lane to the output port of the same name in
the corresponding external PLL.
• Connect the
tx_pll_locked
input pin of the 50G Interlaken IP core to the logical AND of the
pll_locked
output signals of the external PLLs for all of the Interlaken lanes and the inverse of each of
the
pll_cal_busy
signals from the external PLLs.
• Connect the
tx_pll_powerdown
output pin of the 50G Interlaken IP core to the
pll_powerdown
reset
pin of the external PLLs for all of the Interlaken lanes.
User logic must provide the AND function and connections. The following figure provides an example of
one correct method, among many, to implement connection logic. You can also refer to the example
design for example working user logic including one correct method to instantiate and connect an
external PLL.
Figure 2-5: Example Connection of ATX PLL with 50G Interlaken IP Core Using Arria 10 xN Clock
Network
ATX PLL ATX PLL ATX PLL ATX PLL
pll_powerdown
50G Interlaken IP Core
Txvr Block N
Txvr Block N+1
tx_pll_locked
tx_pll_powerdown
tx_serial_clk[11] (Channel 5) (Lane 11)
tx_serial_clk[10] (Channel 4) (Lane 10)
tx_serial_clk[9] (Channel 3) (Lane 9)
tx_serial_clk[8] (Channel 2) (Lane 8)
tx_serial_clk[7] (Channel 1) (Lane 7)
tx_serial_clk[6] (Channel 0) (Lane 6)
tx_serial_clk[5] (Channel 5) (Lane 5)
tx_serial_clk[4] (Channel 4) (Lane 4)
tx_serial_clk[3] (Channel 3) (Lane 3)
tx_serial_clk[2] (Channel 2) (Lane 2)
tx_serial_clk[1] (Channel 1) (Lane 1)
tx_serial_clk[0] (Channel 0) (Lane 0)
pll_locked
pll_cal_busy
tx_serial_clk
(8 Lanes)
Related Information
• Arria 10 External PLL Interface on page 4-3
• 50G Interlaken IP Core Testbench on page 7-1
UG-01140
2015.05.04
Adding the External PLL 2-13
Getting Started With the 50G Interlaken IP Core Altera Corporation
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