Altera 50G Interlaken MegaCore Function - Manual (Page 3)

50G Interlaken IP Core Clock Signals...........................................................................................4-5
IP Core Reset.................................................................................................................................... 4-5
IP Core Reset Sequence with the Reconfiguration Controller.................................................. 4-7
Interleaved and Packet Modes................................................................................................................... 4-7
50G Interlaken IP Core Transmit Path.....................................................................................................4-8
50G Interlaken IP Core Transmit User Data Interface Examples.............................................4-8
50G Interlaken IP Core In-Band Calendar Bits on Transmit Side......................................... 4-12
50G Interlaken IP Core Transmit Path Blocks.......................................................................... 4-13
50G Interlaken IP Core Receive Path......................................................................................................4-14
50G Interlaken IP Core Receive User Data Interface Examples............................................. 4-14
50G Interlaken IP Core RX Errored Packet Handling............................................................. 4-16
In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface......... 4-18
50G Interlaken IP Core Receive Path Blocks............................................................................. 4-19
50G Interlaken MegaCore Function Signals.......................................................5-1
50G Interlaken IP Core Clock Interface Signals......................................................................................5-1
50G Interlaken IP Core Reset Interface Signals.......................................................................................5-2
50G Interlaken IP Core User Data Transfer Interface Signals.............................................................. 5-4
50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals................................... 5-8
50G Interlaken IP Core Management Interface.................................................................................... 5-12
Device Dependent Signals........................................................................................................................ 5-14
Transceiver Reconfiguration Controller Interface Signals.......................................................5-14
Arria 10 External PLL Interface Signals......................................................................................5-15
Arria 10 Transceiver Reconfiguration Interface Signals.......................................................... 5-15
50G Interlaken IP Core Register Map.................................................................6-1
50G Interlaken IP Core Testbench..................................................................... 7-1
50G Interlaken IP Core Testbench Interface Signals..............................................................................7-2
Testbench Simulation Behavior.................................................................................................................7-3
Running the Testbench With the Example Design.................................................................................7-3
Setting Up the Testbench Example................................................................................................7-3
Simulating the Example Design.....................................................................................................7-3
50G Interlaken IP Core Test Features................................................................ 8-1
Internal Serial Loopback Mode..................................................................................................................8-1
External Loopback Mode............................................................................................................................8-1
PRBS Generation and Validation.............................................................................................................. 8-2
Setting up PRBS Mode in Arria V and Stratix V Devices.......................................................... 8-2
Setting up PRBS Mode in Arria 10 Devices..................................................................................8-4
CRC32 Error Injection ............................................................................................................................... 8-7
Advanced Parameter Settings............................................................................. 9-1
Hidden Parameters...................................................................................................................................... 9-1
Required User Clock Frequency.................................................................................................... 9-1
About This MegaCore Function TOC-3
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