Altera 50G Interlaken MegaCore Function - Manual (Page 79)

Advanced Parameter Settings
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2015.05.04
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Advanced users can further customize the 50G Interlaken IP core by modifying hidden parameters that
are not displayed in the 50G Interlaken parameter editor. These parameters can only be modified in the
Verilog RTL instantiation in the generated ilk_core_50g.sv file and the instantiation of the 50G Interlaken
IP core in the top level design file.
The following topics describe the hidden parameters and tell you how to modify their values.
Hidden Parameters on page 9-1
Modifying Hidden Parameter Values on page 9-4
Hidden Parameters
The advanced parameters affect the behavior of the 50G Interlaken MegaCore function.
Note: Altera recommends that you do not modify any RTL parameters that are not listed here. Some
undocumented modifications might overwrite settings you specify in the parameter editor.
To customize your 50G Interlaken MegaCore function, you can modify parameters to specify the
following properties:
Required User Clock Frequency on page 9-1
Counter Reset Bits on page 9-2
Include Temp Sense on page 9-2
RXFIFO Address Width on page 9-2
SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping) on page 9-2
Use ATX or CMU PLL on page 9-4
Lane Profile on page 9-4
Required User Clock Frequency
The
TX_USR_CLK_MHZ
parameter specifies the expected frequency of the input clocks
tx_usr_clk
and
rx_usr_clk
.
The default value of this parameter is 250 MHz. The range of allowed values is 200 MHz to 300 MHz. You
must drive the two input clocks at the frequency specified by this parameter.
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