50g interlaken ip core test features, Internal serial loopback mode, External loopback mode – Altera 50G Interlaken MegaCore Function User Manual
Page 72: 50g interlaken ip core test features -1, Internal serial loopback mode -1, External loopback mode -1
50G Interlaken IP Core Test Features
8
2015.05.04
UG-01140
Your 50G Interlaken IP core supports the following test features:
on page 8-1
The 50G Interlaken IP core supports an internal TX to RX serial loopback mode.
The 50G Interlaken IP core operates correctly in an external loopback configuration.
PRBS Generation and Validation
on page 8-2
Internal Serial Loopback Mode
The 50G Interlaken IP core supports an internal TX to RX serial loopback mode.
To turn on internal serial loopback:
• Reset the IP core by asserting the active low
reset_n
signal.
• After reset completes, set the value of bits [NUM_LANES-1:0] of the
LOOPBACK
register at offset 0x12
to all ones.
Note: Refer to "IP Core Reset" for information about the required wait period for register access.
• Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the
rx_lanes_aligned
output signal. After the RX lanes are aligned, the IP core is in internal serial loopback mode.
Resetting the IP core turns off internal serial loopback. To turn off internal serial loopback:
• Reset the IP core by asserting the active low
reset_n
signal. Resetting the IP core sets the value of bits
[NUM_LANES-1:0] of the
LOOPBACK
register at offset 0x12 to all zeroes.
• Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the
rx_lanes_aligned
output signal. After the RX lanes are aligned, the IP core is in normal operational mode.
External Loopback Mode
The 50G Interlaken IP core operates correctly in an external loopback configuration.
To put the IP core in external loopback mode, connect the TX lanes to the RX lanes of the IP core. This
mode does not require any special programming of the IP core.
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