Altera 50G Interlaken MegaCore Function - Manual (Page 82)

Use ATX or CMU PLL
The USE_ATX parameter specifies whether the transceivers use the ATX PLL or the CMU PLL. If this
parameter has the value of 0, the 50G Interlaken IP core transceivers are configured to use the CMU PLL.
If this parameter has the value of 1, the 50G Interlaken IP core transceivers are configured to use the ATX
PLL.
This parameter is not available in IP core variations that target an Arria 10 device. These variations do not
include a TX PLL. Instead, you must configure an external PLL and connect it to the IP core.
If the transceivers use the ATX PLL, more transceiver block logical channels are available for the eight
Interlaken lanes. However, some lower
pll_ref_clk
frequencies are not available with the ATX PLL.
The default value of this parameter is 0, specifying that the IP core transceivers use the CMU PLL and
have available the full range of
pll_ref_clk
frequencies documented for this input clock.
Related Information
Modifying Hidden Parameter Values on page 9-4
Lane Profile
The LANE_PROFILE parameter specifies the mapping of Interlaken lanes to transceiver logical channels
on one side of the device.
This parameter is not available in IP core variations that target an Arria 10 device.
The Interlaken lane order is fixed: Interlaken Lane 0 maps to the lowest numbered logical channel to
which a lane is mapped; Interlaken Lane 1 maps to the next lowest numbered logical channel to which a
lane is mapped; etc. You determine the side of the device outside the IP core, with pin assignments. Your
pin assignments must be consistent with the value of the LANE_PROFILE parameter.
The default value of this parameter is 24'b000000_000000_101101_101101, for use with the CMU PLL.
This lane profile specifies that the eight 50G Interlaken IP core Interlaken lanes map to the logical
channels in the two bottom transceiver blocks that are consistent with use of the CMU PLL. These logical
channels are logical channels 0, 2, 3, 5, 7, 9, 10, and 12.
If you want to use the ATX PLL, you can set this parameter to specify the use of the full bottom
transceiver block and two channels from the adjacent transceiver block.
Related Information
• Transceiver Logical Channel Numbering on page 2-7
Illustrates the logical channel mapping for the default lane profile.
• Use ATX or CMU PLL on page 9-4
Describes the hidden parameter to specify whether the IP core transceivers use the CMU PLL or the
ATX PLL.
• Modifying Hidden Parameter Values on page 9-4
Modifying Hidden Parameter Values
To modify the value of a hidden parameter, you must edit one or more generated files. Every time you
regenerate the 50G Interlaken IP core, the files are overwritten and you must edit them again.
9-4 Use ATX or CMU PLL
UG-01140
2015.05.04
Altera Corporation Advanced Parameter Settings
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