Altera 50G Interlaken MegaCore Function - Manual (Page 23)

• Pin Assignments on page 2-6
• Arria 10 External PLL Interface Signals on page 5-15
• Arria 10 Transceiver PHY User Guide
Information about the correspondence between PLLs and transceiver channels, and information about
how to configure an external PLL for your own design. You specify the clock network to which the
PLL output connects by setting the clock network in the PLL parameter editor.
Compiling the Full Design and Programming the FPGA
You can use the Start Compilation command on the Processing menu in the Quartus II software to
compile your design. After successfully compiling your design, program the targeted Altera device with
the Programmer and verify the design in hardware.
Related Information
• Quartus II Incremental Compilation for Hierarchical and Team-Based Design
Information about compiling your design. Chapter in volume 1 of the Quartus II Handbook.
• Quartus II Programmer
Information about programming the device. Chapter in volume 3 of the Quartus II Handbook.
2-14 Compiling the Full Design and Programming the FPGA
UG-01140
2015.05.04
Altera Corporation Getting Started With the 50G Interlaken IP Core
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