50g interlaken megacore function signals, 50g interlaken ip core clock interface signals, 50g interlaken megacore function signals -1 – Altera 50G Interlaken MegaCore Function User Manual
Page 47: 50g interlaken ip core clock interface signals -1
50G Interlaken MegaCore Function Signals
5
2015.05.04
UG-01140
The 50G Interlaken MegaCore function communicates with the surrounding design through multiple
external signals.
50G Interlaken IP Core Clock Interface Signals
Table 5-1: 50G Interlaken IP Core Clock Interface
Signal Name
Direction
Width
(Bits)
Description
Clock Ports
pll_ref_clk
Input
1
Transceiver reference clock for the RX transceiver
PLL in IP core variations that target an Arria 10
device. Transceiver reference clock for RX and TX
transceiver PLLs in all other variations.
The 50G Interlaken IP core supports the following
pll_ref_clk
frequencies: 156.25 MHz, 195.3125
MHz, 250 MHz, 312.5 MHz, 390.625 MHz, 500 MHz,
and 625 MHz.
The
pll_ref_clk
input clock frequency must match
the value you specify for the Transceiver reference
clock frequency parameter.
tx_serial_clk
Input
NUM_
LANES–
Clocks for the individual transceiver channels in
50G Interlaken IP core variations that target an Arria
10 device.
clk_tx_common
Output
1
PCS common lane clock driven by the SERDES
transmit PLL. The clock rate is the lane rate divided
by 40 bits. The
clk_tx_common
frequency is
156.25 MHz for 6.25 Gbps per lane.
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