Altera 50G Interlaken MegaCore Function - Manual (Page 6)

• Supports up to 256 logical channels in out-of-the-box configuration.
• Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.
• Supports optional out-of-band flow control blocks.
Related Information
Interlaken Protocol Specification, Rev 1.2
IP Core Supported Combinations of Number of Lanes and Data Rate
Table 1-1: 50G Interlaken IP Core Supported Combinations of Number of Lanes and Data Rate
The 50G Interlaken IP core supports only the following combination of number of lanes and data rate.
Number of Lanes Lane Rate (Gbps)
8 6.25
IP Core Raw Aggregate Bandwidth
The raw aggregate bandwidth of the 50G Interlaken IP core is 8 × 6.25 Gbps = 50 Gbps.
Device Family Support
The following table lists the device support level definitions for Altera IP cores.
Table 1-2: Altera IP Core Device Support Levels
FPGA Device Families
Preliminary support — The core is verified with preliminary timing models for this device family. The IP
core meets all functional requirements, but might still be undergoing timing analysis for the device family. It
can be used in production designs with caution.
Final support — The IP core is verified with final timing models for this device family. The IP core meets all
functional and timing requirements for the device family and can be used in production designs.
The following table shows the level of support offered by the 50G Interlaken MegaCore function for each
Altera device family.
Table 1-3: Device Family Support
Device Family Support
Stratix V (GS, GT, and GX) Final
Arria V (GZ) Final
Arria 10 Preliminary
1-2 IP Core Supported Combinations of Number of Lanes and Data Rate
UG-01140
2015.05.04
Altera Corporation About This MegaCore Function
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