Altera 50G Interlaken MegaCore Function - Manual (Page 73)

PRBS Generation and Validation
The 50G Interlaken IP core supports generation and validation of several predetermined pseudo-random
binary sequences (PRBS) for Interlaken link testing.
Table 8-1: PRBS Polynomials Available in the 50G Interlaken IP Core
Pattern
Name
Polynomial
Defined in
Interlaken
Specification
Available in 50G Interlaken IP Core Variations with
Target Device Family
Arria V or Stratix V Arria 10
PRBS7 x 7 + x 6 + 1 Yes Yes No
PRBS9 x 9 + x 5 +1 No Yes Yes
PRBS15 x 15 + x 14 +1 No No Yes
PRBS23 x 23 + x 18 + 1 Yes Yes Yes
PRBS31 x 31 + x 28 + 1 Yes Yes Yes
For instructions to activate and use the PRBS test feature in your 50G Interlaken IP core IP core, refer to
one of the following two topics:
Setting up PRBS Mode in Arria V and Stratix V Devices on page 8-2
Setting up PRBS Mode in Arria 10 Devices on page 8-4
Setting up PRBS Mode in Arria V and Stratix V Devices
To enable the IP core to generate PRBS output, you must program the relevant hard PCS registers to
enable the PRBS generator clock, to set the test_enable bit, and to select the PRBS polynomial. To enable
the IP core to receive PRBS input, you must program the relevant hard PCS registers to enable the PRBS
receiver clock, to set the test_enable bit, and to select the expected PRBS polynomial. If you perform your
PRBS testing in loopback mode, you must enable the IP core to both generate and receive PRBS
sequences.
This section describes the register values you must program. For instructions to program the registers that
activate the PRBS test feature in your Arria V or Stratix V 50G Interlaken IP core, refer to the hard PCS
register programming instructions in the Native PHY IP Core chapter for your target device family and in
the Transceiver Reconfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide.
8-2 PRBS Generation and Validation
UG-01140
2015.05.04
Altera Corporation 50G Interlaken IP Core Test Features
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