Altera 50G Interlaken MegaCore Function - Manual (Page 16)

Transceiver Logical Channel Numbering
In Arria V and Stratix V devices, logical channel numbering starts from zero. The logical channel
numbering starts at the bottom of the die with logical channel 0 and continues in physical pin order
through the four ordered transceiver blocks on the same side of the device. Each data channel and TX PLL
has its own dedicated reconfiguration interface with an assigned logical channel.
In Arria 10 devices, you control the mapping of Interlaken lanes directly in the Arria 10 Native PHY IP
core that is included in the 50G Interlaken IP core.
In Arria V and Stratix V devices, you can control the logical channel assignments in the IP core. You
typically assign lanes to match the logical channel numbering. However, the default Interlaken lane
assignment does not assign a lane to Channel 1 or Channel 4 in a transceiver block, leaving either
available for the CMU PLL. You can use the information in the following table to map the lanes to their
default logical channel numbering. The logical channel numbering always starts at the bottom of a
transceiver block.
Table 2-1: Transceiver Logical Channel Numbering
The default expected mapping of logical channels to Interlaken lanes in Arria V and Stratix V devices.
Transceiver Block Number Logical Channel Number in
Device
Direction Interlaken Lane Number in
IP Core
27 TX PLL 3
3
26
TX
RX
25
TX
RX
24
TX
RX
23
TX
RX
22
TX
RX
21
TX
RX
UG-01140
2015.05.04
Transceiver Logical Channel Numbering 2-7
Getting Started With the 50G Interlaken IP Core Altera Corporation
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