NEC uPD78P078 - Manual (Page 24)

24
LIST OF FIGURES (4/9)
Figure No. Title Page
10-14 8-Bit Timer Control Register Settings for PWM Output Operation .......................................... 264
10-15 PWM Output Operation Timing (Active High Setting) ............................................................... 265
10-16 PWM Output Operation Timings (CRn0 = 00H, Active High Setting) ...................................... 265
10-17 PWM Output Operation Timings (CRn0 = FFH, Active High Setting) ..................................... 266
10-18 PWM Output Operation Timings (CRn0 Changing, Active High Setting) ................................ 266
10-19 8-bit Timer Registers 5 and 6 Start Timings ............................................................................. 267
10-20 External Event Counter Operation Timings ............................................................................... 267
10-21 Timings after Compare Register Change during Timer Count Operation ............................... 268
11-1 Watch Timer Block Diagram ...................................................................................................... 271
11-2 Timer Clock Select Register 2 Format ...................................................................................... 272
11-3 Watch Timer Mode Control Register Format ............................................................................ 273
12-1 Watchdog Timer Block Diagram ................................................................................................ 277
12-2 Timer Clock Select Register 2 Format ...................................................................................... 279
12-3 Watchdog Timer Mode Register Format ................................................................................... 280
13-1 Remote Controlled Output Application Example ....................................................................... 283
13-2 Clock Output Control Circuit Block Diagram ............................................................................. 284
13-3 Timer Clock Select Register 0 Format ...................................................................................... 286
13-4 Port Mode Register 3 Format ..................................................................................................... 287
14-1 Buzzer Output Control Circuit Block Diagram ........................................................................... 289
14-2 Timer Clock Select Register 2 Format ...................................................................................... 291
14-3 Port Mode Register 3 Format ..................................................................................................... 292
15-1 A/D Converter Block Diagram .................................................................................................... 294
15-2 A/D Converter Mode Register Format ....................................................................................... 297
15-3 A/D Converter Input Select Register Format ............................................................................ 298
15-4 External Interrupt Mode Register 1 Format ............................................................................... 299
15-5 A/D Converter Basic Operation .................................................................................................. 301
15-6 Relationships between Analog Input Voltage and A/D Conversion Result ............................. 302
15-7 A/D Conversion by Hardware Start ............................................................................................ 303
15-8 A/D Conversion by Software Start ............................................................................................. 304
15-9 Example of Method of Reducing Current Consumption in Standby Mode .............................. 305
15-10 Analog Input Pin Disposition ...................................................................................................... 306
15-11 A/D Conversion End Interrupt Request Generation Timing ..................................................... 307
15-12 Handling of AV DD
Pin .................................................................................................................. 307
16-1 D/A Converter Block Diagram .................................................................................................... 310
16-2 D/A Converter Mode Register Format ....................................................................................... 312
16-3 Use Example of Buffer Amplifier ................................................................................................ 314