NEC uPD78P078 - Manual (Page 459)

459
CHAPTER 20 SERIAL INTERFACE CHANNEL 2
Figure 20-2. Baud Rate Generator Block Diagram
TPS3 TPS2 TPS1 TPS0
Internal Bus
MDL3 MDL2 MDL1 MDL0
Baud Rate Generator
Control Register
4
TXE
CSIE2
5-Bit
Counter
Selector
Selector
Decoder
1/2 Selector
Terminal Clock
1/2
Selector
Receive Clock
Match
Match
MDL0 to MDL3
5-Bit
Counter
RXE
Start Bit Detection
Selector f
xx
to f
xx
/2 10
TPS0 to TPS3
SCK
CSCK
ASCK/SCK2/P72
4
4
Start Bit
Sampling Clock