NEC uPD78P078 User Manual
Page 324
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078 SUBSERIES)
324
SBI mode
<6>
<5>
4
3
2
1
0
<7>
Symbol
CSIM0 CSIE0 COI
WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input Clock to SCK0 pin from off-chip
8-bit timer register 2 (TM2) output
0
0
SCK0 (CMOS
input/output)
R/W
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
1
CSIM00
x
0
1
FF60H 00H R/W
Note 1
Address After Reset R/W
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
Mode
Start Bit
SI0/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
x
1
0
x
0
x
0
0
x
0
x
0
0
1
1
Note 3 Note 3
Note 3 Note 3
MSB
P25 (CMOS
input/output)
SB0 (N-ch
open-drain
input/output)
SB1 (N-ch
open-drain
input/output)
P26 (CMOS
input/output)
1
MSB
LSB
1
x
0
0
0
1
Note 2
3-wire serial
l/O mode
SI0
Note 2
(Input)
SO0
(CMOS output)
SCK0 (CMOS
input/output)
2-wire serial
l/O mode
0
SCK0 (N-ch
open-drain
input/output)
1
1
1
x
0
x
0
0
x
0
x
0
0
1
1
Note 3 Note 3
Note 3 Note 3
MSB
P25 (CMOS
input/output)
SB0 (N-ch
open-drain
input/output)
SB1 (N-ch
open-drain
input/output)
P26 (CMOS
input/output)
Note 2
WUP
0
1
Wake-up Function Control
Note 4
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1)
matches the slave address register data in SBI mode
R/W
COI
0
1
Slave Address Comparison Result Flag
Note 5
Slave address register not equal to serial I/O shift register 0 data
Slave address register equal to serial I/O shift register 0 data
R
CSIE0
0
1
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enable
R/W
Figure 17-4. Serial Operating Mode Register 0 Format
Notes 1. Bit 6 (COI) is a read-only bit.
2. Can be used as P25 (CMOS input/output) when used only for transmission.
3. Can be used freely as port function.
4. When using the wake-up function (WUP = 1), set bit 5 (SIC) of the interrupt timing specify
register (SINT) to 0.
5. When CSIE0 = 0, COI becomes 0.
Remark
x
: Don’t care
PMxx : Port mode register
Pxx
: Port output latch