NEC uPD78P078 - Manual (Page 408)

408
CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078Y Subseries)
18.4.5 Cautions on use of I 2 C bus mode
(1) Start condition output (master)
The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL
pin to high in order to output a start condition signal. Set the bit 3 (CLC) of the interrupt timing specify register
(SINT) to drive the SCL pin high.
After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output.
If it is the master device which outputs the start condition and stop condition signals, confirm that CLD is set
to 1 after setting CLC to 1; a slave device may have set SCL to low (wait state).
Figure 18-24. Start Condition Output
SCL
CLC
CMDT
CLD
SDA0 (SDA1)