2 operation list – NEC uPD78P078 User Manual
Page 584
584
CHAPTER 28 INSTRUCTION SET
28.2 Operation List
Instruction
Mnemonic
Operands
Byte
Clock
Operation
Flag
Group
Note 1
Note 2
Z AC CY
8-bit data
MOV
r, #byte
2
4
—
r
←
byte
transfer
saddr, #byte
3
6
7
(saddr)
←
byte
sfr, #byte
3
—
7
sfr
←
byte
A, r
Note 3
1
2
—
A
←
r
r, A
Note 3
1
2
—
r
←
A
A, saddr
2
4
5
A
←
(saddr)
saddr, A
2
4
5
(saddr)
←
A
A, sfr
2
—
5
A
←
sfr
sfr, A
2
—
5
sfr
←
A
A, !addr16
3
8
9 + n
A
←
(addr16)
!addr16, A
3
8
9 + m
(addr16)
←
A
PSW, #byte
3
—
7
PSW
←
byte
x
x
x
A, PSW
2
—
5
A
←
PSW
PSW, A
2
—
5
PSW
←
A
x
x
x
A, [DE]
1
4
5 + n
A
←
(DE)
[DE], A
1
4
5 + m
(DE)
←
A
A, [HL]
1
4
5 + n
A
←
(HL)
[HL], A
1
4
5 + m
(HL)
←
A
A, [HL + byte]
2
8
9 + n
A
←
(HL + byte)
[HL + byte], A
2
8
9 + m
(HL + byte)
←
A
A, [HL + B]
1
6
7 + n
A
←
(HL + B)
[HL + B], A
1
6
7 + m
(HL + B)
←
A
A, [HL + C]
1
6
7 + n
A
←
(HL + C)
[HL + C], A
1
6
7 + m
(HL + C)
←
A
XCH
A, r
Note 3
1
2
—
A
↔
r
A, saddr
2
4
6
A
↔
(saddr)
A, sfr
2
—
6
A
↔
sfr
A, !addr16
3
8
10
+n+m
A
↔
(addr16)
A, [DE]
1
4
6
+n+m
A
↔
(DE)
A, [HL]
1
4
6
+n+m
A
↔
(HL)
A, [HL + byte]
2
8
10
+n+m
A
↔
(HL + byte)
A, [HL + B]
2
8
10
+n+m
A
↔
(HL + B)
A, [HL + C]
2
8
10
+n+m
A
↔
(HL + C)
Notes 1. For instructions that access the internal high-speed RAM area or perform no data access
2. For instructions that access an area other than the internal high-speed RAM area
3. Except when “r = A”
Remarks 1. One clock in the “Clock” columns is equal to one cycle of the CPU clock (f
CPU
) selected by the processor
clock control register (PCC).
2. The values in the “Clock” column assumes that the internal ROM area contains programs.
3. n indicates wait cycles to be inserted when an external expansion memory area is read from.
4. m indicates wait cycles to be inserted when an external expansion memory area is written to.