Document Outline

• Table of Contents
• List Of Figures
• List of Tables
• 1. Package Pin/Ball Assignments and Configurations
  • 1.1 64-Ball Wafer-Level Chip Scale Package (WLCSP)
  • 1.2 65-Ball Fine-Pitch Ball Grid Array (FBGA) Package
  • 1.3 Pin/Ball Descriptions
  • 1.4 Digital Pin/Ball I/O Configurations
• 2. Typical Connection Diagram
  • 2.1 Low-Profile Charge-Pump Capacitors
  • 2.2 Ceramic Capacitor Derating
• 3. Characteristic and Specifications
  • Recommended Operating Conditions
  • Absolute Maximum Ratings
  • DC Electrical Characteristics
  • Analog Input To Serial Port Characteristics
  • Stereo-ADC and Dual-Digital-Mic Digital Filter Characteristics
  • Thermal Overload Detect Characteristics
  • ASRC Digital Filter Characteristics
  • Mic BIAS Characteristics
  • Serial Port to Stereo HP Output Characteristics
  • Serial Port to Stereo Line Output Characteristics
  • Serial Port to Mono Ear Speaker Output Characteristics
  • Serial Port-to-Mono Speakerphone Output Characteristics
  • Serial Port to Mono Speakerphone Line Output Characteristics
  • Stereo/Mono DAC Interpolation and On-Chip Digital/Analog Filter Characteristics
  • Power Consumption
  • Digital Interface Specifications and Characteristics
  • Switching Specifications—Power, Reset, and Master Clocks
  • Switching Specifications—Digital Mic Interface
  • Switching Specifications—Serial Ports—I²S Format
  • Switching Specifications—Serial Ports—PCM Format
  • Switching Specifications—Control Port
• 4. Applications
  • 4.1 Overview
    • 4.1.1 Basic Architecture
    • 4.1.2 Line and Microphone Inputs
    • 4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers)
    • 4.1.4 Digital Mixer
    • 4.1.5 Power Management
  • 4.2 Internal Master Clock Generation
  • 4.3 Thermal Overload Notification
  • 4.4 Pseudodifferential Outputs
  • 4.5 Class H Amplifier
    • 4.5.1 Power Control Options
    • 4.5.2 Power Supply Transitions
    • 4.5.3 Efficiency
  • 4.6 DAC Limiter
  • 4.7 Analog Output Current Limiter
  • 4.8 Serial Ports
    • 4.8.1 Power Management
    • 4.8.2 I/O
    • 4.8.3 High-impedance Mode
    • 4.8.4 Master and Slave Timing
    • 4.8.5 Serial Port Sample Rates and Master Mode Settings
    • 4.8.6 Formats
    • 4.8.7 Mono/Stereo
    • 4.8.8 Data Bit Depths
  • 4.9 Asynchronous Sample Rate Converters (ASRCs)
  • 4.10 Input Paths
    • 4.10.1 Input Path Source Selection and Powering
    • 4.10.2 Digital Microphone (DMIC) Interface
  • 4.11 Digital Mixer
    • 4.11.1 Mono and Stereo Paths
    • 4.11.2 Mixer Input Attenuation Adjustment
    • 4.11.3 Powered-Down Mixer Inputs
    • 4.11.4 Avoiding Mixer Clipping
    • 4.11.5 Mixer Attenuation Values
  • 4.12 Recommended Operating Procedures
    • 4.12.1 Initial Power-Up Sequence
    • 4.12.2 Power-Up Sequence (xSP to HP/LO)
    • 4.12.3 Power-Down Sequence (xSP to HP/LO)
    • 4.12.4 Recommended Sequence for Modification of the MCLK Signal
    • 4.12.5 Microphone Enabling/Switching Sequence
    • 4.12.6 Final Power-Down Sequence
  • 4.13 Using MIC2_SDET as Headphone Plug Detect
  • 4.14 Headphone Plug Detect and Mic Short Detect
  • 4.15 Interrupts
  • 4.16 Control Port Operation
    • 4.16.1 I²C Control
  • 4.17 Fast Start Mode
  • 4.18 Headphone High-Impedance Mode
• 5. Register Quick Reference
• 6. Register Description
  • 6.1 Fast Mode Enable (Address 00h)
    • 6.1.1 Test Bits
  • 6.2 Device ID A and B (Address 01h), C and D (Address 02h), and E (Address 03h) (Read Only)
    • 6.2.1 Device I.D. (Read Only)
  • 6.3 Revision ID (Address 05h) (Read Only)
    • 6.3.1 Alpha Revision (Read Only)
    • 6.3.2 Metal Revision (Read Only)
  • 6.4 Power Control 1 (Address 06h)
    • 6.4.1 Power Down ADC x
    • 6.4.2 Power Down Digital Mic x
    • 6.4.3 Discharge Filt+ Capacitor
    • 6.4.4 Power Down Device
  • 6.5 Power Control 2 (Address 07h)
    • 6.5.1 Power Down MICx Bias
    • 6.5.2 Power Down VSP
    • 6.5.3 Power Down ASP SDOUT Path
    • 6.5.4 Power Down ASP SDIN Path
    • 6.5.5 Power Down XSP SDOUT Path
    • 6.5.6 Power Down XSP SDIN Path
  • 6.6 Power Control 3 and Thermal Overload Threshold Control (Address 08h)
    • 6.6.1 Thermal Overload Threshold Settings
    • 6.6.2 Power Down Thermal Sense
    • 6.6.3 Power Down Speakerphone Line Output
    • 6.6.4 Power Down Ear Speaker
    • 6.6.5 Power Down Speakerphone
    • 6.6.6 Power Down Line Output
    • 6.6.7 Power Down Headphone
  • 6.7 Charge Pump Frequency and Class H Configuration (Address 09h)
    • 6.7.1 Charge Pump Frequency
    • 6.7.2 Adaptive Power Adjustment
  • 6.8 Output Load, Mic Bias, and MIC2 Short Detect Configuration (Address 0Ah)
    • 6.8.1 VP Supply Minimum Voltage Setting
    • 6.8.2 Speakerphone Light Load Mode Enable
    • 6.8.3 Mic Bias Output Control
    • 6.8.4 Short Detect Automatic Mute Control
  • 6.9 Digital Mic and Master Clock Control (Address 0Bh)
    • 6.9.1 Digital Mic Shift Clock Divide Ratio
    • 6.9.2 Master Clock Source Selection
    • 6.9.3 Master Clock Divide Ratio
    • 6.9.4 Master Clock Disable
  • 6.10 XSP Control (Address 0Ch)
    • 6.10.1 Tristate XSP Interface
    • 6.10.2 XSP Digital Interface Format
    • 6.10.3 XSP PCM Interface Mode
    • 6.10.4 XSP PCM Format Bit Order
    • 6.10.5 XSP SCLK Source Equals MCLK
  • 6.11 XSP Master Mode Clocking Control (Address 0Dh)
    • 6.11.1 XSP Master/Slave Mode
    • 6.11.2 XSP Master Mode Clock Control Dividers
  • 6.12 ASP Control (Address 0Eh)
    • 6.12.1 Tristate ASP Interface
    • 6.12.2 ASP Sample Rate
    • 6.12.3 ASP SCLK Source Equals MCLK
  • 6.13 ASP Master Mode Clocking Control (Address 0Fh)
    • 6.13.1 ASP Master/Slave Mode
    • 6.13.2 ASP Master Mode Clock Control Dividers
  • 6.14 VSP Control (Address 10h)
    • 6.14.1 Tristate VSP Interface
    • 6.14.2 VSP Digital Interface Format
    • 6.14.3 VSP PCM Interface Mode
    • 6.14.4 VSP PCM Format Bit Order
    • 6.14.5 VSP SDIN Location
    • 6.14.6 VSP SCLK Source Equals MCLK
  • 6.15 VSP Master Mode Clocking Control (Address 11h)
    • 6.15.1 VSP Master/Slave Mode
    • 6.15.2 VSP Master Mode Clock Control Dividers
  • 6.16 VSP and XSP Sample Rate (Address 12h)
    • 6.16.1 VSP Sample Rate
    • 6.16.2 XSP Sample Rate
  • 6.17 Miscellaneous Input and Output Path Control (Address 13h)
    • 6.17.1 Digital Swap/Mono
    • 6.17.2 Input Path Channel B=A
    • 6.17.3 PREAMP and PGA Channel B=A
    • 6.17.4 PGA Soft-Ramp
    • 6.17.5 Analog Zero Cross
    • 6.17.6 Digital Soft-Ramp
    • 6.17.7 Analog Output Soft Ramp
  • 6.18 ADC/Input Path Control (Address 14h)
    • 6.18.1 PGA x Input Select
    • 6.18.2 Boost x
    • 6.18.3 Invert ADCx Signal Polarity
    • 6.18.4 Input Path x Digital Mute
  • 6.19 Mic PreAmp and PGA Volume Control: Channel A (Mic 1, Address 15h) and Channel B (Mic 2, Address 16h)
    • 6.19.1 Mic PREAMP x Volume
    • 6.19.2 PGAx Volume
  • 6.20 Input Path x Digital Volume Control: Channel A (Address 17h) and B (Address 18h)
    • 6.20.1 Input Path x Digital Volume Control
  • 6.21 Playback Digital Control (Address 19h)
    • 6.21.1 Speakerphone [A], Ear Speaker/Speakerphone Line Output [B] (SES) Playback Channels B=A
    • 6.21.2 Headphone/Line Output (HL) Playback Channels B=A
    • 6.21.3 Limiter Soft-Ramp Disable
    • 6.21.4 Ear Speaker/Speakerphone Line Output Digital Mute
    • 6.21.5 Speakerphone Digital Mute
    • 6.21.6 Headphone/Line Output (HL) x Digital Mute
  • 6.22 Headphone/Line Output (HL) x Digital Volume Control: Channel A (Address 1Ah) and B (Address 1Bh)
    • 6.22.1 Headphone/Line Output (HL) x Digital Volume Control
  • 6.23 Speakerphone Out [A] Digital Volume Control (Address 1Ch)
    • 6.23.1 Speakerphone Out [A] Digital Volume Control
  • 6.24 Ear Speaker/Speakerphone Line Output (ESL) [B] Digital Volume Control (Address 1Dh)
    • 6.24.1 Ear Speaker/Speakerphone Line Output (ESL) [B] Digital Volume Control
  • 6.25 Headphone Analog Volume Control: Channel A (Address 1Eh) and B (Address 1Fh)
    • 6.25.1 Headphone x Analog Mute
    • 6.25.2 Headphone x Analog Volume Control
  • 6.26 Line Output Analog Volume Control: Channel A (Address 20h) and B (Address 21h)
    • 6.26.1 Line Output x Analog Mute
    • 6.26.2 Line Output x Analog Volume Control
  • 6.27 Stereo Input Path Advisory Volume (Address 22h)
    • 6.27.1 Stereo Input Path Advisory Volume
  • 6.28 XSP Input Advisory Volume (Address 23h)
    • 6.28.1 XSP Input Advisory Volume
  • 6.29 ASP Input Advisory Volume (Address 24h)
    • 6.29.1 ASP Input Advisory Volume
  • 6.30 VSP Input Advisory Volume (Address 25h)
    • 6.30.1 VSP Input Advisory Volume
  • 6.31 Limiter Attack Rate Headphone/Line Output (HL) (Address 26h)
    • 6.31.1 Limiter Attack Rate HL
  • 6.32 Limiter Control, Release Rate Headphone/Line Output (HL) (Address 27h)
    • 6.32.1 Peak Detect and Limiter HL
    • 6.32.2 Peak Signal Limit All Channels HL
    • 6.32.3 Limiter Release Rate HL
  • 6.33 Limiter Min/Max Thresholds Headphone/Line Output (HL) (Address 28h)
    • 6.33.1 Limiter Maximum Threshold HL
    • 6.33.2 Limiter Cushion Threshold HL
  • 6.34 Limiter Attack Rate Speakerphone [A] (Address 29h)
    • 6.34.1 Limiter Attack Rate Speakerphone [A]
  • 6.35 Limiter Control, Release Rate Speakerphone [A] (Address 2Ah)
    • 6.35.1 Peak Detect and Limiter Speakerphone [A]
    • 6.35.2 Peak Signal Limit All Channels Speakerphone
    • 6.35.3 Limiter Release Rate Speakerphone [A]
  • 6.36 Limiter Min/Max Thresholds Speakerphone [A] (Address 2Bh)
    • 6.36.1 Limiter Maximum Threshold Speakerphone [A]
    • 6.36.2 Limiter Cushion Threshold Speakerphone [A]
  • 6.37 Limiter Attack Rate Ear Speaker/Speakerphone Line Output (ESL) [B]
    • 6.37.1 Limiter Attack Rate ESL [B]
  • 6.38 Limiter Control, Release Rate Ear Speaker/Speakerphone Line Output (ESL) [B] (Address 2Dh)
    • 6.38.1 Peak Detect and Limiter ESL [B]
    • 6.38.2 Limiter Release Rate ESL [B]
  • 6.39 Limiter Min/Max Thresholds Ear Speaker/Speakerphone Line Output (ESL) [B]
    • 6.39.1 Limiter Maximum Threshold ESL [B]
    • 6.39.2 Limiter Cushion Threshold ESL [B]
  • 6.40 ALC Enable and Attack Rate AB (Address 2Fh)
    • 6.40.1 ALC for Channels A and B (ALCx)
    • 6.40.2 ALC Attack Rate for Channels A and B
  • 6.41 ALC Release Rate AB (Address 30h)
    • 6.41.1 ALC Release Rate for Channels A and B
  • 6.42 ALC Threshold AB (Address 31h)
    • 6.42.1 ALC Maximum Threshold for Channels A and B
    • 6.42.2 ALC Minimum Threshold for Channels A and B
  • 6.43 Noise Gate Control AB (Address 32h)
    • 6.43.1 Noise Gate Enable for Channels A and B (NGx)
    • 6.43.2 Noise gate Threshold and Boost for Channels A and B
    • 6.43.3 Noise Gate Delay Timing for Channels A and B
  • 6.44 ALC and Noise Gate Misc Control (Address 33h)
    • 6.44.1 ALC Ganging of Channels A and B
    • 6.44.2 Noise Gate Ganging of Channels A and B
    • 6.44.3 ALCx Soft-Ramp Disable
    • 6.44.4 ALCx Zero Cross Disable
  • 6.45 Mixer Control (Address 34h)
    • 6.45.1 VSP Mixer Output Stereo
    • 6.45.2 XSP Mixer Output Stereo
    • 6.45.3 Mixer Soft-Ramp Enable
    • 6.45.4 Mixer Soft-Ramp Step Size/Period
  • 6.46 Stereo Mixer Input Attenuation (Addresses 35h through 54h)
    • 6.46.1 Stereo Mixer Input Attenuation
  • 6.47 Mono Mixer Controls (Address 55h)
    • 6.47.1 Speakerphone (SPK) Mixer, ASP Select
    • 6.47.2 Speakerphone (SPK) Mixer, XSP Select
    • 6.47.3 Ear Speaker/Speakerphone Line Output (ESL) Mixer, ASP Select
    • 6.47.4 ESL Mixer, Auxiliary Serial Port (XSP) Select
  • 6.48 Mono Mixer Input Attenuation (Addresses 56h through 5Dh)
    • 6.48.1 Mono Mixer Input Attenuation
  • 6.49 Interrupt Mask Register 1 (Address 5Eh)
  • 6.50 Interrupt Mask Register 2 (Address 5Fh)
  • 6.51 Interrupt Status Register 1 (Address 60h)
    • 6.51.1 MIC2 Short Detect
    • 6.51.2 Thermal Overload Detect
    • 6.51.3 Digital Mixer Overflow
    • 6.51.4 Input Path x Overflow
  • 6.52 Interrupt Status Register 2 (Address 61h)
    • 6.52.1 Voice ASRC Data Out Lock
    • 6.52.2 Voice ASRC Data In Lock
    • 6.52.3 Audio ASRC Data Out Lock
    • 6.52.4 Audio ASRC Data In Lock
    • 6.52.5 Auxiliary ASRC Data Out Lock
    • 6.52.6 Auxiliary ASRC Data In Lock
  • 6.53 Fast Mode 1 (Address 7Eh)
    • 6.53.1 Fast Mode Bits 15:8
  • 6.54 Fast Mode 2 (Address 7Fh)
    • 6.54.1 Fast Mode Bits 7:0
• 7. PCB Layout Considerations
  • 7.1 Power Supply
  • 7.2 Grounding
  • 7.3 Layout With Fine-Pitch, Ball-Grid Packages
• 8. Performance Data
  • 8.1 Analog Input Path Attributes
    • 8.1.1 PGA Analog Volume Nonlinearity (DNL and INL)
  • 8.2 Analog Mic/Line ADC and Digital Mic Input Path Attributes
    • 8.2.1 Input Path Digital LPF Response
    • 8.2.2 Input Path Digital HPF Response
  • 8.3 Core Circuitry Attributes
    • 8.3.1 ASRC Attributes
  • 8.4 Analog Output Paths Attributes
    • 8.4.1 DAC Digital LPF Response
    • 8.4.2 DAC HPF Response
    • 8.4.3 Output Analog Volume Nonlinearity (DNL and INL)
    • 8.4.4 Startup Times
• 9. Parameter Definitions
• 10. Package Dimensions
  • 10.1 WLCSP Package
  • 10.2 FBGA Package
• 11. Thermal Characteristics
• 12. Ordering Information
• 13. References
• 14. Revision History