Pwm (pulse width modulator) register list, Programming example, Operational overview – Cirrus Logic EP73xx User Manual
Page 108
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EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
PWM Interface
12
PWM (Pulse Width Modulator) Register List
Programming Example
;*****************************************************************************
; Example turns on PWM drive O. System powered from AC source for
; 15/16 duty cycle
;*****************************************************************************
PMPCON_AC
EQU
0xF0
;
ldr
r0, =0x80000000
mov
r1, =PMPCON_AC
str
r1, [r0,#0x400]
;
Operational Overview
The device operates from the internal PLL at 96 kHz (117.6 kHz at a CPU speed of 90
MHz), and 101.6 kHz if the external 13 MHz clock is used. These signals are intended
for use as drivers for external DC-DC converters. The PWM has a programmable
duty cycle and a built-in detection feedback pin which can be used to enable or
disable the drive.
The PMPCON register is programmed to active the PWM Drive pins to generate a
square wave with a duty cycle that can be varied from 1 pulse in 16, to 15 pulses in 16.
Programming the value of 8 into the Drive pin registers will create a 50% duty cycle
output.
The drive pins (
Drive[1:0]
) are sensed for polarity at power on reset. If the pin is high,
the PWM signal will be active low. If low, the pin will be active high.
The
Drive[0]
has the conditional capability of sensing whether the system is battery
powered or supplied by an external source by monitoring
BATOK
and
nEXTPWR
.
Based on the activity of these pins, the EP73xx will look at the appropriate settings in
the PMPCON register.
BATOK
is active high.
nEXTPWR
is active low.
The PWM feedback pins (
FB[1:0]
) determine if the PWM is to be enabled or disabled
the PWM drive. If the value is 0, the corresponding PWM drive is turned off, and if
the value is 1, the PWM remains enabled. They do not disable the internal clock that
sources the PWM drives.
Note: To maximize power savings, the drive fields should be used to disable the
PWMs, instead of the FB pins. The clocks that source the PWMs are disabled
when the drive ratio fields are cleared.
Table 12-1: PWM (Pulse Width Modulator) Registers
Address
Name
Type
Size
Description
Page
0x8000.0400
PMPCON
R/W
12
Pump (PWM) Control Register