Cirrus Logic EP73xx - Manual (Page 91)

EP7309/11/12 User’s Manual - DS508UM4 9-1
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Copyright Cirrus Logic, Inc. 2003
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9
Chapter 9
9 LCD Interface
Introduction
The LCD interface provides all the necessary control signals to interface directly to a
single panel multiplexed LCD. It is programmable for different line lengths, bits-per-
pixel and refresh rates. The frame buffer can reside in either SDRAM and RAM
memory. 1/4 VGA support is typical but 1/2 VGA (monochrome) support is possible
assuming a refresh rate above 40 Hz is not required. When the CPU speed is set to 74
MHz, the bus speed will be 36 MHz. When the CPU speed is set to 90 Mhz, the bus
speed will be 45 MHz. Calculations made using the formulas in this chapter must
take CPU and bus speed variables into account.
Features
• 1-2-4 bpp (bits per pixel)
• Programmable panel size to a maximum of 1024x256 at 4 bps
• Relocatable Frame Buffer (SRAM or SDRAM)
• Programmable refresh rates
• 16 gray scale values
• Color screen interface capability
LCD Register List
Table 9-1: LCD Registers
Address Name Type Size Description Page
0x8000.02C0 LCDCON R/W 32 LCD Control Register page 9-7
0x8000.0580 PALLSW R/W 32 Least Sig. Word Palette page 9-8
0x8000.540 PALMSW R/W 32 Most Sig Word Palette page 9-8
0x8000.1000 FBADDR R/W 4
Frame Buffer Start Address
Register
page 9-9