Cirrus Logic EP73xx - Manual (Page 45)

EP7309/11/12 User’s Manual - DS508UM4 3-3
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Copyright Cirrus Logic, Inc. 2003
Timers
33
3
Prescale Mode
Any value written to TC1 or TC2 is automatically re-loaded when the counter
underflows. Any value written to TC1 or TC2 will be decremented on the second
edge of the selected clock. Setting bit 4 or 6 in SYSCON1 for TC1 and TC2
respectively, will initiate prescale mode.
RTC Timer
The RTC timer is derived from the RTC clock. The timer interface creates a 1 Hz tick
that can be controlled by the RTCDR (RTC data register). This 32-bit read/write
register value corresponds to the number of 1 Hz ticks and will be incremented on the
next rising edge of the 1 Hz clock. Any value may be written to this register.
The interrupt driven from this clock comes from the RTCMR (RTC Match Register).
Once the value in the match register actually “matches” the value in the data register,
the interrupt will assert.
Timer Register Descriptions
Timer Counter 1 Data Register (TC1D)
Address: 0x8000.0300, Read/Write
Definition: The timer counter 1 data register is a 16-bit read/write register
which sets and reads data to TC1. Any value written will be
decremented on the next rising edge of the clock.
Timer Counter 2 Data Register(TC2D)
Address: 0x8000.0340, Read/Write
Definition: The timer counter 2 data register is a 16-bit read/write register
which sets and reads data to TC2. Any value written will be
decremented on the next rising edge of the clock
Real Time Clock Data Register (RTCDR)
Address: 0x8000.0380, Read/Write
Definition: The Real Time Clock data register is a 32-bit read/write register,
which sets and reads the binary time in the RTC. Any value written
will be incremented on the next rising edge of the 1 Hz clock. This
register is reset only by
nPOR .