Cirrus Logic EP73xx - Manual (Page 30)

2-4 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
CPU Core
2
Operational Overview
Using the Von Neumann (load/store) architecture, the ARM720T core has a three
stage instruction pipeline to increase the speed of the instruction execution within the
processor. The fetch-decode-execute of concurrent instructions are done in parallel
requiring approximately 1.9 CPI (cycles per instruction).
The core provides a 8 Kbytes unified cache and a memory management unit (MMU).
The MMU supports a two-level page table arrangement and controls the cache and
write buffer for each page created.
ARM720T core has 37 32-bit registers: 1-program counter, 1-current program status
register, 5-saved program status registers, 30-general purpose registers. The core also
supports 16 co-processor registers for control of the on-chip cache, MMU, and buffers.
The core supports two instruction sets, ARM and Thumb for full 32-bit or 16-bit
instruction decoding. State switching between ARM and Thumb, and register
assignments for each, are detailed in the ARM720T document provided by ARM. The
core supports both big as well as little-endian modes.
The core contains an embedded debug architecture. The 5-pin JTAG port will allow
the host system to convert debugger commands into JTAG commands for the
purpose of hardware control to do the following:
• Set breakpoints and watchpoints
• Halt the ARM processor
• Access internal registers
• Access system memory
MMU
The MMU (Memory Management Unit) does the following
• Translates virtual addresses to physical addresses
• Controls memory access permissions, cache and write buffer accesses for
each page.
The MMU consists of a TLB (translation look aside buffer) and hardware for page
table accesses as well as the access control logic.
Memory is divided by the MMU in the following manner:
• Sections: 1 Mbyte memory blocks
• Large Page: 64 Kbytes memory blocks which allows mapping of large
region with only a single entry in the TLB.
• Small Page: 4 Kbytes memory blocks
Based on the entry for the section or page, the cache and write buffer will be either
enabled or disabled for that region of memory.