Cirrus Logic EP73xx - Manual (Page 134)

16-10 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
DAI/CODEC/SSI2
16
will begin one clock, or more, after the last byte transferred and will resume at least
one clock prior to the first frame sync assertion. To disable the clock, the TX section is
turned off.
Note: In Master mode, the EP73xx does not support the discontinuous clock.
Error Conditions
RX FIFO overflows are detected and conveyed via a status bit in the SYSFLG2
register. This register should be accessed at periodic intervals by the application
software. The status register should be read each time the RX FIFO interrupts are
generated. At this time the error condition (i.e., overrun flag) will indicate that an
error has occurred but cannot convey which byte contains the error. Writing to the
SRXEOF register location clears the overrun flag. TX FIFO underflow condition is
detected and conveyed via a bit in the SYSFLG2 register, which is accessed by the
application software. A TX underflow error is cleared by writing data to be
transmitted to the TX FIFO.
Clock Polarity
Clock polarity is fixed. TX data is presented on the bus on the rising edge of the clock.
Data is latched into the receiving device on the falling edge of the clock. The TX pin is
held in a tristate condition when not transmitting.
CODEC Sound Interface
The CODEC interface allows direct connection of a telephony type codec to the
EP73XX. It provides all the necessary clocks and timing pulses. It also performs a
parallel to serial conversion or vice versa on the data stream to or from the external
codec device. The interface is full duplex and contains two separate data FIFOs (16
deep by 8-bits wide, one for the receive data, another for the transmit data).
Data is transferred to or from the codec at 64 kbits/s. The data is either written to or
read from the appropriate 16-byte FIFO. If enabled, a codec interrupt (CSINT) will be
generated after every 8 byte are transferred (FIFO half full/empty). This means the
interrupt rate will be every 1 ms, with a latency of 1 ms.
Transmit and receive modes are enabled by asserting high both the CDENRX and
CDENTX codec enable bits in the SYSCON1 register.
Note: Both the CDENRX and CDENTX enable bits should be asserted in tandem for
data to be transmitted or received. The reason for this is that the interrupt
generation will occur 1 ms after one of the FIFOs is enabled. For example: If the
receive FIFO gets enabled first and the transmit FIFO at a later time, the
interrupt will occur 1 ms after the receive FIFO is enabled. After the first interrupt
occurs, the receive FIFO will be half full. However, it will not be possible to know
how full the transmit FIFO will be since it was enabled at a later time. Thus, it is
possible to unintentionally overwrite data already in the transmit FIFO
After the CDENRX and CDENTX enable bits are asserted, the corresponding FIFOs
become enabled. When both FIFOs are disabled, the FIFO status flag CRXFE is set
and CTXFF is cleared so that the FIFOs appear empty. Additionally, if the CDENTX
bit is low, the
PCMOUT output is disabled. Asserting either of the two enable bits